Lesson Plan

Lesson Plan
Grade: Date: 17/01/2026
Subject: Computer Science
Lesson Topic: Understand the purpose of components in Von Neumann architecture
Learning Objective/s:
  • Describe the purpose of each component in the Von Neumann architecture (CPU, CU, ALU, Memory, I/O, Bus).
  • Explain the fetch‑decode‑execute cycle and how the components interact during program execution.
  • Analyse how sharing a single memory and bus creates the Von Neumann bottleneck.
  • Apply the cycle to a simple ADD instruction to predict data flow and results.
  • Compare the basic model with modern enhancements such as caches and pipelines.
Materials Needed:
  • Projector and screen
  • Printed diagram of the Von Neumann architecture
  • Worksheet with component purpose table and instruction‑cycle tasks
  • Laptops with a basic assembly‑language simulator
  • Whiteboard and markers
  • Exit‑ticket slips
Introduction:

Begin with a quick poll: “What parts of a computer do you think make it ‘think’?” Connect students’ prior knowledge of CPUs and memory to the new focus on how these parts cooperate. Explain that by the end of the lesson they will be able to trace a complete instruction through the system and identify where performance limits arise.

Lesson Structure:
  1. Do‑now (5’) – Students list known computer components; teacher collects a quick mind‑map.
  2. Mini‑lecture (10’) – Using the projected diagram, describe each component’s purpose and introduce the bus system.
  3. Guided demonstration (12’) – Walk through the fetch‑decode‑execute cycle on a sample ADD instruction with the simulator, highlighting data movement on the bus.
  4. Pair activity (10’) – Learners complete a worksheet mapping each step of the cycle to the relevant component and bus line.
  5. Whole‑class discussion (8’) – Discuss the “Von Neumann bottleneck” and modern mitigations (caches, pipelines).
  6. Exit ticket (5’) – Each student writes one way modern computers reduce the bottleneck.
Conclusion:

Recap the role of each component and the sequence of the instruction cycle, emphasizing how the shared bus can limit speed. Collect exit tickets to gauge understanding and assign a short homework: research one modern architecture feature that addresses the bottleneck and prepare a one‑sentence summary for the next class.