Understand the purpose of components in Von Neumann architecture

Computer Architecture – Von Neumann Model (Cambridge IGCSE/AS‑Level)

Learning Objective

Explain the purpose of each component in the Von Neumann architecture, describe how the components interact during the fetch‑decode‑execute cycle, and relate the model to wider syllabus topics such as micro‑processors, performance factors, instruction sets, embedded systems, data representation, data transmission, I/O, software, the Internet and cyber‑security.

1. The Von Neumann Architecture

• Single shared memory – programme instructions and data are stored together in the main store (RAM).
• Sequential execution – the CPU normally processes instructions in order, unless a branch/jump changes the flow.
• Common bus system – one set of address, data and control buses connects CPU, memory and I/O, producing the classic “Von Neumann bottleneck”.

2. Main Internal Components of the CPU

3. The Fetch‑Decode‑Execute Cycle (syllabus terminology)

1. Fetch
   • CU places the address from the Program Counter (PC) on the address bus.
   • Address is loaded into the Memory Address Register (MAR).
   • Memory returns the instruction on the data bus → stored in Memory Data Register (MDR).
   • MDR → Current Instruction Register (CIR).
2. Decode
   • CU reads the opcode in the CIR, determines which part of the CPU (ALU, registers, etc.) is needed.
   • If an operand resides in memory, its address is placed in the MAR.
3. Execute
   • For data‑processing: ALU operates on the ACC (or other registers) and stores the result back in the ACC.
   • For memory‑access: data moves between MDR and the address held in MAR via the data bus.
4. Update PC
   • Sequential instruction – PC is incremented to the next address.
   • Branch/jump – PC is loaded with the new address supplied by the instruction.

4. CPU Performance Factors (syllabus point 3)

• Clock speed – number of cycles per second (Hz). Faster clocks → more instructions per second.
• Number of cores – each core can run its own instruction stream, enabling true parallelism.
• Cache memory
  • Small, very fast memory on the CPU chip.
  • L1 cache is fastest, L2/L3 are larger but slower.
  • Stores frequently used instructions or data, reducing main‑memory accesses.
• Pipeline & separate instruction/data caches – modern techniques that overlap fetch, decode and execute stages, mitigating the Von Neumann bottleneck.

5. Microprocessor (syllabus point 1b)

A microprocessor is a CPU fabricated on a single integrated circuit (IC). It contains the CU, ALU, registers and bus‑control logic in one chip, making computers smaller, cheaper and more reliable compared with earlier multi‑chip implementations.

6. Instruction Set (syllabus point 4)

• Collection of machine‑code commands a CPU can recognise and execute.
• Each instruction consists of an opcode and, where required, operand address(es) or immediate data.
• Typical IGCSE‑level examples:
  • LOAD addr – copy data from memory address addr into the ACC.
  • STORE addr – copy the ACC contents to memory address addr.
  • ADD addr – add the value at addr to the ACC.
  • SUB addr – subtract the value at addr from the ACC.
  • JUMP addr – set the PC to addr (branch).

7. Embedded Systems (syllabus point 5)

A specialised computer built into a larger device to perform a limited set of tasks.

• Microwave oven controller – reads keypad, controls magnetron, displays time.
• Digital watch – time‑keeping, alarms, display.
• ABS (anti‑lock braking) system – monitors wheel‑speed sensors, modulates brake pressure.
• Smart thermostat – reads temperature sensor, drives heating/cooling relay.

8. Data Representation (syllabus cross‑reference)

9. Data Transmission (syllabus cross‑reference)

• Packet structure – header (address, control), payload, trailer (checksum).
• USB & Ethernet – common wired interfaces; basic signalling and speed categories.
• Error detection – parity bit, checksum, CRC.
• Simple encryption – Caesar cipher, XOR masking – introductory ideas for data security.

10. Input/Output Devices & Storage (syllabus cross‑reference)

11. Software (syllabus cross‑reference)

Interrupts – hardware or software signals that temporarily suspend the current instruction sequence, allowing the CPU to respond to urgent events (e.g., I/O completion, timer).

12. The Internet & Its Uses (syllabus cross‑reference)

• URL, HTTP/HTTPS – request/response model for web pages.
• DNS – translates domain names to IP addresses.
• Client‑server architecture – browsers (clients) request services from web servers.
• Basic concepts of cloud storage and online collaboration.

13. Cyber‑Security (syllabus cross‑reference)

• Authentication – passwords, biometrics.
• Encryption – symmetric (AES) vs. asymmetric (RSA) basics.
• Malware – viruses, worms, ransomware.
• Firewalls & anti‑virus software – protect against unauthorised access.

14. Algorithms, Programming & Logic (syllabus cross‑reference)

• Algorithm design – clear, finite sequence of steps; use of flowcharts or pseudocode.
• Boolean logic – AND, OR, NOT, XOR; truth tables; basis for decision making in programmes.
• Control structures – sequential, selection (if‑else, switch), iteration (for, while).
• Data structures – arrays, simple records; indexing and addressing.
• SQL basics – SELECT, INSERT, UPDATE, DELETE for relational databases.

15. Sample Calculation – Using the FDE Registers

Instruction: ADD 1000 – add the value stored at memory address 1000 to the value already in the ACC and store the result back in the ACC.

1. Fetch
   • PC = 200 (address of ADD 1000).
   • PC → address bus → MAR.
   • Memory returns binary instruction → MDR → CIR.
2. Decode
   • CU reads opcode “ADD” and operand address “1000” from CIR.
3. Execute
   • Operand address 1000 placed on address bus → MAR.
   • Memory sends data at 1000 (e.g., 7) → MDR.
   • MDR (7) and ACC (5) fed to ALU → 5 + 7 = 12.
   • Result (12) stored back in ACC.
4. Update PC
   • PC incremented to 201 for the next instruction.

Result: ACC now holds the binary representation of 12.

16. Revision Questions

1. Why does the Von Neumann architecture use a single memory for both programme instructions and data? Discuss the advantage and the bottleneck it creates.
2. Describe the role of the Program Counter (PC) during each stage of the fetch‑decode‑execute cycle.
3. Identify the three registers directly involved in the fetch part of the cycle and state the function of each.
4. List three factors that affect CPU performance and give a brief example of how each improves speed.
5. Define a microprocessor and contrast it with a multi‑chip CPU implementation.
6. What is an instruction set? Provide two example instructions and explain what each does.
7. Give two examples of embedded systems and describe the specific task each performs.
8. Explain the “Von Neumann bottleneck” and name one modern technique used to reduce its impact.
9. Convert the binary number 11010110 to decimal and hexadecimal.
10. Briefly describe how a parity bit can detect a single‑bit error in data transmission.
11. What is the difference between system software and application software? Give one example of each.
12. Write a short pseudocode algorithm that reads ten numbers, stores them in an array, and outputs the largest value.

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