Lesson Plan

• Describe each phase (fetch, decode, execute, store) of the fetch‑decode‑execute cycle.
• Explain the role of the PC, IR, CU, ALU and registers during the cycle.
• Interpret a timing diagram to identify when control signals change.
• Compare sequential execution with the concept of pipelining.

• Projector or interactive whiteboard
• Slide deck showing the cycle and timing diagram
• Printed handout with component table and cycle steps
• Worksheet with a simple assembly instruction
• Laptop with a CPU simulation tool (e.g., Logisim)
• Markers and sticky notes for group flow‑chart activity

Begin with a short video clip that shows a computer running a program instantly, prompting students to wonder how the CPU accomplishes this. Review prior knowledge of memory and basic CPU parts. State that by the end of the lesson they will be able to describe every step of the instruction cycle and identify the function of each component.

1. Do‑Now (5'): Quick quiz on CPU components displayed on the board.
2. Mini‑lecture (10'): Present the fetch phase with a block diagram; highlight PC and address bus.
3. Guided practice (10'): Decode a sample instruction on the handout, labeling opcode and operands.
4. Interactive simulation (15'): Students use the CPU simulator to step through the execute phase.
5. Timing diagram analysis (10'): In pairs, label the control‑signal changes on a printed diagram.
6. Consolidation activity (5'): Groups create a flow‑chart of the full cycle using sticky notes.
7. Exit ticket (5'): Write one sentence describing the PC’s role in the cycle.

Recap the four main phases and the key components that drive each step. Collect exit tickets to gauge understanding, then assign a homework task: research how pipelining overlaps multiple fetch‑decode‑execute cycles and prepare a short paragraph.