Describe the fetch–decode–execute cycle

Computer Architecture – The Fetch‑Decode‑Execute Cycle

Learning objective

Describe the fetch‑decode‑execute (FDE) cycle, name the role of each CPU component, register, bus and clock pulse, and relate the cycle to instruction sets, embedded systems and the storage hierarchy. Use this knowledge to answer AO1 (recall), AO2 (explain) and AO3 (apply) questions in the Cambridge IGCSE 0478 exam.

1. What the FDE cycle does

The FDE cycle (also called the instruction cycle) is the repeatable three‑phase process a CPU uses to execute every machine‑level instruction:

1. Fetch – obtain the next instruction from memory.
2. Decode – interpret the opcode and identify any operands.
3. Execute – carry out the operation and store the result (or change the program flow).

The cycle continues until a HALT instruction is reached.

2. Core CPU components and their function in the cycle

3. Buses and the clock pulse

• Address bus – carries the address from the MAR (or PC) to RAM.
• Data bus – carries the instruction or operand between RAM and the MDR/IR, and later between the ALU and registers.
• Control bus – carries timing and control signals such as MEM_READ, MEM_WRITE, ALU_OP, PC_LOAD, etc., generated by the CU.
• Clock pulse – a regular electrical pulse that synchronises the three phases. In a single‑cycle design each phase occupies one clock tick; in a multi‑cycle design a phase may span several ticks.

4. Instruction set – definition and examples

An instruction set is the complete collection of machine‑level commands a CPU can execute. Each instruction consists of an opcode (the operation) and, optionally, operand specifiers (register names, immediate values or memory addresses).

Typical simple instructions used in IGCSE questions:

ADD   R1, R2          ; R1 ← R1 + R2
SUB   R3, #5          ; R3 ← R3 – 5
LD    ACC, 0x3F       ; Load the byte at address 0x3F into the accumulator
ST    ACC, 0x40       ; Store the accumulator’s content at address 0x40
JMP   0x20            ; PC ← 0x20 (unconditional branch)
BRZ   R0, 0x30        ; If R0 = 0 then PC ← 0x30 (conditional branch)
IN    R0, PORT1       ; Read a byte from peripheral PORT1 into R0
OUT   PORT2, ACC      ; Write the accumulator’s content to peripheral PORT2
HALT                 ; Stop execution

5. Detailed step‑by‑step description of the cycle

1. Fetch phase
   • PC → MAR (address bus).
   • CU asserts MEM_READ on the control bus.
   • Memory places the instruction on the data bus; it is loaded into MDR.
   • MDR → IR (instruction register).
   • PC is incremented (normally PC ← PC + 1) unless the instruction is a branch/jump.
2. Decode phase
   • CU examines the opcode stored in IR.
   • Control signals are generated to select the required operand registers or to activate the MAR for a memory operand.
   • If the instruction requires a second memory read (e.g., load from a data address), the address is placed on MAR and a new MEM_READ cycle is performed.
3. Execute phase
   • The ALU carries out the operation (add, subtract, logical AND, shift, etc.) on the selected operands.
   • Result is written to the ACC or a general‑purpose register.
   • For branch/jump instructions the CU updates the PC according to the condition flags.
4. Store result (if required)
   • If the instruction writes a value to memory, the target address is placed on MAR, the data on MDR, and MEM_WRITE is asserted.
   • Otherwise the result remains in a register for use by a later instruction.
5. I/O transfer (optional)
   • When an instruction involves an I/O device, the I/O‑CU mediates the transfer between the data bus and the peripheral.
   • Examples: IN R0, PORT1 or OUT PORT2, ACC.
6. Repeat
   • The next clock pulse starts a new fetch phase using the address now held in the PC.

6. Timing diagram (conceptual)

7. Connection to embedded systems and the storage hierarchy

• Even the smallest micro‑controllers in embedded devices follow the same FDE cycle, though they often implement a reduced instruction set (RISC) and may combine fetch and decode to speed up execution.
• Primary storage (RAM) holds the program and data that the CPU fetches during the cycle.
• Read‑Only Memory (ROM) contains the bootstrap code that loads the first instructions into RAM.
• Cache memory sits between the CPU and RAM, providing faster access to frequently used instructions and thereby shortening the fetch phase.
• Virtual memory (used in larger systems) extends the address space onto secondary storage, but the CPU still fetches instructions from the address space presented by the memory‑management unit.

8. Why this matters for the Cambridge assessment (AO1‑AO3)

• AO1 – Knowledge: Recall the names and functions of the PC, MAR, MDR, IR, ACC, registers, CU, ALU and the three buses.
• AO2 – Understanding: Explain how the control unit generates signals such as MEM_READ and ALU_OP to move data through the cycle.
• AO3 – Application: Use the step‑by‑step description to trace the execution of a given instruction (e.g., ADD R1,R2) or to predict the effect of a branch instruction on the PC.

9. Extension box (optional – for higher‑order thinking)

10. Key points to remember

• The FDE cycle consists of three logical phases (fetch, decode, execute) that repeat for every instruction.
• The PC, MAR, MDR, IR, ACC and general‑purpose registers each have a defined role in moving and holding data.
• Three buses (address, data, control) and a clock pulse coordinate the flow of information.
• The Control Unit orchestrates the cycle by generating the appropriate control signals.
• Branch and jump instructions modify the PC, changing the sequential flow of execution.
• All computers – from desktop processors to tiny embedded micro‑controllers – use the fetch‑decode‑execute concept.
• Modern designs may overlap cycles (pipelining), but the fundamental sequence remains the same.