Lesson Plan

• Describe the operation and characteristic equations of SR and JK flip‑flops.
• Explain the difference between a level‑sensitive SR latch and an edge‑triggered JK flip‑flop.
• Apply truth tables and excitation tables to determine required inputs for desired state transitions.
• Design a simple circuit using SR and JK flip‑flops for a given function.

• Projector or interactive whiteboard
• Printed handouts with SR and JK truth/excitation tables
• Digital logic simulation software (e.g., Logisim)
• Breadboard, NAND/NOR gate ICs, and JK flip‑flop ICs (e.g., 74LS76)
• Worksheets for practice problems

Begin with a quick poll: “What device stores a single bit of information?” Connect this to students’ prior knowledge of latches from earlier lessons. Explain that today they will master two fundamental flip‑flops and be able to choose the right one for sequential circuits. Success will be measured by correctly completing truth‑table exercises and a short design task.

1. Do‑now (5'): Quick quiz on binary bits and the concept of a bistable device.
2. Mini‑lecture (10'): Define flip‑flops, present SR latch operation, truth table and characteristic equation.
3. Guided practice (12'): In pairs, fill out the SR truth table on handouts; discuss the forbidden S=R=1 state.
4. Simulation demo (8'): Show SR latch behavior with Logisim, emphasising level‑sensitivity.
5. JK flip‑flop exploration (12'): Introduce JK inputs, toggle operation, edge‑triggering; complete JK truth and excitation tables.
6. Application task (8'): Design a 2‑bit binary counter using JK flip‑flops; share solutions and perform a rapid check for understanding.

Recap the key differences between SR and JK flip‑flops and why JK is preferred for synchronous designs. Students complete an exit ticket: “Write one advantage of the JK flip‑flop over the SR latch.” For homework, assign a worksheet requiring students to derive excitation tables for a given state‑machine diagram.