Show understanding of a flip-flop (SR, JK)

15.2 Boolean Algebra and Logic Circuits – Flip‑Flops

Learning Objective

Students will be able to:

• Explain the operation of SR and JK flip‑flops, including their timing behaviour.
• Derive and use the characteristic equations and excitation (transition) tables.
• Analyse Karnaugh‑map simplifications for the next‑state logic.
• Identify the practical uses of SR, JK, D and T flip‑flops in synchronous sequential circuits.

1. Introduction to Flip‑Flops

• A flip‑flop is a bistable multivibrator that stores one binary digit (bit).
• It has two stable output states, usually denoted Q = 0 and Q = 1.
• State changes occur only on a triggering event:
  • Level‑sensitive latch: output follows inputs while an enable (or clock) level is active.
  • Edge‑triggered flip‑flop: output changes only on a specified clock edge (rising or falling).
• Flip‑flops are the fundamental building blocks of registers, counters, memory cells and finite‑state machines (FSMs).

2. SR (Set‑Reset) Flip‑Flop

2.1 Truth Table (NAND‑based, active‑low inputs)

S	R	Qnext	Comments
0	0	Q (no change)	Memory condition
0	1	1	Set
1	0	0	Reset
1	1	Invalid	Both outputs would be 0 – forbidden

2.2 Characteristic Equation

For a NAND‑based SR latch (active‑low inputs) the next state is

$$Q_{\text{next}} = \overline{S}\;+\;R\,Q$$

where S and R are the active‑low set and reset signals, and Q is the present state.

2.3 Karnaugh‑Map Derivation

2.4 Gate‑Level Circuit

2.5 Key Points

• The SR latch is level‑sensitive; its output follows the inputs while the enable (or clock) is active.
• The combination S = R = 1 is illegal and must be avoided in any practical design.
• Using NOR gates gives the same functionality with active‑high inputs (S and R true = 1).

3. JK Flip‑Flop

3.1 Truth Table (positive‑edge triggered)

J	K	Qnext	Operation
0	0	Q (no change)	Memory
0	1	0	Reset
1	0	1	Set
1	1	\overline{Q}	Toggle

3.2 Characteristic Equation

$$Q_{\text{next}} = J\,\overline{Q}\;+\;\overline{K}\,Q$$

3.3 Karnaugh‑Map Derivation

3.4 Gate‑Level Diagram (master‑slave, positive‑edge)

3.5 Timing Diagram (positive‑edge trigger)

3.6 Excitation (Transition) Table

Current Q	Next Q+	J	K	Explanation
0	0	0	X	Hold (K may be 0 or 1)
0	1	1	X	Set
1	0	X	1	Reset
1	1	X	0	Hold

“X” denotes a “don’t‑care” condition – either value of that input will produce the required transition.

3.7 Level‑Sensitive vs Edge‑Triggered Summary

• SR latch: level‑sensitive; output follows inputs while the enable is asserted.
• JK flip‑flop (master‑slave): edge‑triggered; output changes only on the active clock transition, eliminating race conditions in synchronous designs.

4. Other Common Flip‑Flops

4.1 D (Data) Flip‑Flop

D	Qnext	Operation
0	0	Reset
1	1	Set

Characteristic equation:

$$Q_{\text{next}} = D$$

Uses: simple data storage, shift registers, and as the basic building block for edge‑triggered memory cells.

4.2 T (Toggle) Flip‑Flop

T	Qnext	Operation
0	Q	Hold
1	\overline{Q}	Toggle

Characteristic equation:

$$Q_{\text{next}} = T\;\overline{Q} + \overline{T}\;Q$$

Commonly used in binary counters and frequency‑division circuits (divide‑by‑2, divide‑by‑4, …).

5. Comparison of SR and JK Flip‑Flops

Aspect	SR Flip‑Flop	JK Flip‑Flop
Invalid Input Combination	S = R = 1 (undefined)	J = K = 1 → defined toggle
Triggering	Level‑sensitive (requires gating for synchronisation)	Edge‑triggered (master‑slave) – ideal for synchronous circuits
Typical Use in Counters	Needs extra gating to obtain toggle behaviour	Toggle mode makes it the natural choice for binary counters
Complexity	Two NAND/NOR gates	Four NAND gates + clock gating (more gates, but more functionality)
Common Applications	Debounce circuits, simple set‑reset storage	Registers, synchronous state machines, frequency division

6. Practical Applications

• Registers & RAM cells – SR for simple set‑reset storage; JK or D for edge‑triggered register stages.
• Frequency division – A JK flip‑flop wired in toggle mode (or a T flip‑flop) acts as a divide‑by‑2 circuit.
• Finite‑State Machines – Flip‑flops hold the present state; JK or D are typically used for synchronous state updates.
• Debounce circuits – An SR latch can hold a stable output while a mechanical switch settles.
• Ripple and synchronous counters – Cascading T or JK flip‑flops produces binary count sequences.

7. Summary

The SR flip‑flop introduces the basic set‑reset concept but suffers from an illegal input condition. The JK flip‑flop removes this limitation by defining a toggle operation, and when realised as a master‑slave arrangement it provides edge‑triggered behaviour essential for reliable synchronous design. Mastery of truth tables, characteristic equations, Karnaugh‑map simplifications, excitation tables and timing considerations equips students to design robust sequential circuits and to select the most appropriate flip‑flop (SR, JK, D, T) for a given application.