Computer Science – 4.1 Central Processing Unit (CPU) Architecture | e-Consult

The CPU communicates with memory using three main buses: the address bus, the data bus, and the control bus. Each bus plays a distinct and crucial role in facilitating data transfer.

Address Bus: This bus carries the memory address of the location the CPU wants to access. The number of lines in the address bus determines the maximum amount of memory that can be addressed. For example, a 32-bit address bus can address 2³² bytes (4GB) of memory.

Data Bus: This bus carries the actual data being transferred between the CPU and memory. The width of the data bus (e.g., 8-bit, 16-bit, 32-bit, 64-bit) determines how many bits of data can be transferred simultaneously. A wider data bus allows for faster data transfer.

Control Bus: This bus carries control signals that coordinate the data transfer. These signals tell the memory (and the CPU) what operation to perform. Common control signals include:

• Read signal: Indicates the CPU wants to read data from memory.
• Write signal: Indicates the CPU wants to write data to memory.
• Memory Request (MREQ): Signals the memory that the CPU is requesting access.
• Memory Ready (MRD): Signals the memory that it is ready to respond to a request.

Fetching Instructions and Data: When the CPU needs to fetch an instruction from memory, it places the memory address of the instruction onto the address bus. Simultaneously, it asserts the Read signal on the control bus. The memory then responds by placing the data (the instruction) onto the data bus. The CPU reads the data from the data bus and stores it in its instruction register.

Storing Results: When the CPU needs to store data into memory, it places the memory address onto the address bus and asserts the Write signal on the control bus. The CPU then places the data to be stored onto the data bus. The memory receives the data and stores it at the specified address.