Computer Science – 15.2 Boolean Algebra and Logic Circuits | e-Consult

SR Flip-Flop: The SR flip-flop is a basic sequential logic circuit with two inputs: Set (S) and Reset (R).

• Operation: When S is asserted (typically high), the flip-flop transitions to a '1' state. When R is asserted (typically high), it transitions to a '0' state. If both S and R are asserted simultaneously, the output state is undefined (often considered a metastable state).
• Truth Table:

  S	R	Q(t+1)
  0	0	Q(t)
  0	1	0
  1	0	1
  1	1	Undefined

• Advantages: Simple design, easy to understand.
• Disadvantages: The 'S' and 'R' inputs can conflict, leading to an undefined state. This makes it unsuitable for applications requiring reliable state transitions.
• Suitability: Limited use in practical digital circuits due to the undefined state. May be used in specific applications where the undefined state is acceptable or can be managed.

JK Flip-Flop: The JK flip-flop addresses the problem of the SR flip-flop by providing a third input, J (Justify), which eliminates the undefined state.

• Operation:

  • When J=0 and K=0, the flip-flop holds its current state.
  • When J=0 and K=1, the flip-flop resets to '0'.
  • When J=1 and K=0, the flip-flop sets to '1'.
  • When J=1 and K=1, the flip-flop toggles its state (flips from '0' to '1' or '1' to '0').

• Truth Table:

  J	K	Q(t+1)
  0	0	Q(t)
  0	1	0
  1	0	1
  1	1	!Q(t)

• Advantages: Eliminates the undefined state of the SR flip-flop. Provides a clear and predictable state transition.
• Disadvantages: Slightly more complex than the SR flip-flop.
• Suitability: Widely used in digital circuits due to its reliability and predictable behavior. Suitable for a broad range of applications, including registers, counters, and memory elements.