Explain the difference between Programmable ROM (PROM), Erasable Programmable ROM (EPROM) and Electrically Erasable Programmable ROM (EEPROM)

3.1 Computers and Their Components

Learning Objective

Explain the difference between Programmable ROM (PROM), Erasable Programmable ROM (EPROM) and Electrically Erasable Programmable ROM (EEPROM), and place these memories in the wider context of the Cambridge International AS & A‑Level Computer Science syllabus.

1. Quick Overview of the Required Hardware Topics

• Memory hierarchy

  • Primary (volatile) – Cache (SRAM), Main memory (DRAM)
  • Secondary (non‑volatile) – ROM families, magnetic disks, optical media, flash

• Registers (CPU internal storage)

  Register	Purpose
  Program Counter (PC)	Holds address of next instruction to fetch
  Memory Address Register (MAR)	Transfers address between CPU and memory bus
  Memory Data Register (MDR)	Transfers data to/from memory
  Accumulator (ACC)	Primary arithmetic/logic operand register
  General‑Purpose Registers (GPRs)	Temporary storage for intermediate results
  Status/Flag Register	Holds condition flags (Zero, Carry, Overflow, etc.)

• CPU architecture (Von Neumann model)

  • Fetch‑decode‑execute cycle driven by a clock
  • ALU performs arithmetic and logical operations
  • Control Unit generates control signals for the bus, registers and memory
  • Stored‑program concept – the first instruction is fetched from a fixed ROM location (usually address 0)

• Bus structure

  Bus type	Function	Typical width
  Address bus	Carries memory addresses from CPU to memory/I/O	16‑32 bits (AS) / 32‑64 bits (A‑Level)
  Data bus	Transfers actual data between CPU, memory and peripherals	8‑64 bits depending on architecture
  Control bus	Signals such as Read/Write, Clock, Interrupt Request (IRQ)	Variable, usually a few lines

• I/O devices & embedded systems

  • Keyboard, display, storage, sensors, actuators
  • Micro‑controllers contain configuration registers and firmware stored in ROM/EEPROM

• Logic‑gate fundamentals

  Gate	Symbol	Truth table (A B → Y)
  AND	&	00→0, 01→0, 10→0, 11→1
  OR	≥1	00→0, 01→1, 10→1, 11→1
  NOT	¬	0→1, 1→0
  NAND	⊼	inverse of AND
  NOR	⊽	inverse of OR
  XOR	⊕	01→1, 10→1, 00→0, 11→0

  ROM cells are built from MOSFET transistors, which are themselves realisations of these basic logic functions.

• Interrupt handling

  • Hardware IRQ lines (e.g., from keyboard, timer)
  • Software interrupts (system calls)
  • Prioritisation and vector tables are often stored in ROM/EEPROM

2. ROM Families and Where PROM/EPROM/EEPROM Fit

• ROM (Read‑Only Memory) – non‑volatile; retains data without power.
• Sub‑families:

  • Mask ROM – programmed during silicon fabrication; cannot be altered.
  • PROM – one‑time programmable after manufacture.
  • EPROM – erasable with ultraviolet (UV) light; re‑programmable.
  • EEPROM – electrically erasable; byte‑wise or bit‑wise re‑programming.
  • Flash memory – block‑wise EEPROM; used in USB sticks, SSDs, BIOS/UEFI chips.

3. Detailed Comparison of PROM, EPROM and EEPROM

4. How Each Type Works – Underlying Principles

4.1 Programmable ROM (PROM)

• Array of tiny fusible metal links (one per bit).
• 1 = link intact (low resistance); 0 = link blown (high resistance).
• Programming performed once with a PROM programmer that sends a high‑current pulse (~100 mA) through the selected links, permanently melting them.
• Because the physical fuse is destroyed, data cannot be altered or erased.

4.2 Erasable Programmable ROM (EPROM)

• Each bit is a floating‑gate MOSFET.

  • Control gate (CG) connects to the external circuit.
  • Floating gate (FG) is isolated by a thin oxide; electrons stored here raise the transistor’s threshold voltage.

• Programming (write): Apply ~20 V to the CG while the source is grounded; electrons tunnel through the oxide onto the FG, representing a logical 0.
• Erasing: Expose the whole chip to UV light (≈ 253 nm). Photons give enough energy to discharge the FG, returning every cell to logical 1.
• Erasure is global – the entire device is cleared at once.

4.3 Electrically Erasable Programmable ROM (EEPROM)

• Also built from floating‑gate MOSFETs, but both program and erase are performed electrically.

  • Erase a byte (or even a single bit) by applying a reverse voltage (~‑20 V) to the CG, pulling electrons off the FG.
  • Program uses the same high‑voltage tunnelling technique as EPROM.

• Selective erase means only the required locations are changed – faster and reduces wear.
• Can be re‑programmed while the circuit remains in‑system (in‑circuit programming).

5. Position of PROM/EPROM/EEPROM in the Memory Hierarchy & System Start‑up

• Level 1 – Cache (SRAM): Very fast, volatile, holds temporary data.
• Level 2 – Main memory (DRAM): Larger, slower, volatile.
• Level 3 – Non‑volatile storage:

  • ROM families (Mask ROM, PROM, EPROM, EEPROM, Flash) – store firmware, boot code, configuration data.
  • Secondary storage (magnetic disks, SSDs, optical media) – hold user programs and data.

At power‑up the CPU fetches the first instruction from a fixed ROM address (usually 0x0000). This instruction typically resides in a PROM/EPROM/EEPROM and contains the bootstrap routine that initialises the hardware, performs a memory‑test, and loads the operating system from secondary storage.

6. Links to Other Syllabus Areas

6.1 Language Translators (AS 5.2)

Firmware stored in ROM is written in assembly or machine code. The source code is assembled (or compiled) into binary op‑codes, which are then programmed into PROM/EPROM/EEPROM. Understanding the translation process helps students see why the code must be exact and why errors require re‑programming the ROM.

6.2 Data Representation (A‑Level 13)

• ROM addresses and contents are expressed in binary and hexadecimal (e.g., 0x3FF for the last byte of a 1 KB EPROM).
• Bit‑patterns stored in ROM may represent instruction op‑codes, lookup tables, or fixed data such as character fonts.

6.3 Communication & Protocols (A‑Level 14)

Boot firmware often implements low‑level protocols (UART, SPI, I²C) that enable the CPU to communicate with peripherals during start‑up. The protocol handling code resides in ROM/EEPROM, illustrating the close relationship between memory technology and communication concepts.

6.4 Security, Privacy & Data Integrity (AS 6 & A‑Level 17)

• ROM provides immutable code – useful for secure‑boot where the initial code must not be tampered with.
• Modern EEPROM/Flash can store cryptographic keys, digital certificates, and version numbers; the CPU verifies signatures before handing control to the operating system.
• Write‑once PROM can be used for “root of trust” values that never change.

6.5 Hardware & Virtual Machines (A‑Level 15)

The BIOS/UEFI stored in EEPROM can be regarded as a small virtual machine: it interprets hardware configuration, performs POST (Power‑On Self‑Test), and then hands control to the OS loader. Understanding this helps students see the abstraction layers from hardware up to operating systems.

6.6 Algorithms (A‑Level 19)

Simple algorithms are often used to read/write EEPROM. Example (pseudo‑code) for reading a version number:

address = 0x00FF      // EEPROM location for firmware version
version = EEPROM_READ(address)
IF version < required_version THEN
DISPLAY "Update required"
END IF

This demonstrates array indexing, conditionals and I/O – core algorithmic ideas applied to hardware.

7. Example Use‑Cases

8. Summary Comparison

1. Re‑usability: PROM – one‑time; EPROM – reusable after full UV erase; EEPROM – reusable after selective electrical erase.
2. Erase method: PROM – none; EPROM – UV light (entire chip); EEPROM – electrical voltage (byte/bit‑wise).
3. Endurance: PROM – N/A; EPROM – ~10³–10⁴ cycles; EEPROM – ~10⁵–10⁶ cycles.
4. Physical package: EPROM includes a quartz window; PROM and EEPROM are opaque.
5. Programming/erase speed: PROM – single ms (once); EPROM – ms per byte, erase takes seconds‑minutes; EEPROM – µs‑ms per byte, no separate erase step.
6. Typical use‑case: PROM – permanent firmware; EPROM – occasional firmware revisions; EEPROM – frequent field updates and secure‑boot data.

9. Key Take‑aways

• PROM – one‑time programmable using fusible links; permanent and inexpensive.
• EPROM – uses floating‑gate MOSFETs; whole‑chip UV erase makes it reusable, but erase time is long.
• EEPROM – electrically erasable and re‑programmable; supports selective erase, in‑system programming, and high endurance.
• All three are non‑volatile and belong to the ROM family of the memory hierarchy, supplying the firmware that boots the CPU and may also store security keys, configuration data, or small lookup tables.
• Understanding these memories connects directly to other syllabus topics: registers and the fetch‑execute cycle, binary data representation, low‑level communication protocols, language translation, and security mechanisms such as secure boot.