Show understanding of the purpose and role of registers, including the difference between general purpose and special purpose registers

4.1 Central Processing Unit (CPU) Architecture – Registers

Learning objective

Show understanding of the purpose and role of registers, including the difference between general‑purpose and special‑purpose registers, and how they are used in the fetch‑decode‑execute cycle, addressing modes, instruction‑set design and CPU performance.

Why a CPU needs registers

• Registers are the fastest storage locations inside the CPU – they sit on the processor’s datapath and can be accessed in a single clock cycle.
• They hold data, addresses or control information that the processor is currently working with, thereby minimising costly accesses to main memory.
• Fast register access enables the control unit to coordinate the fetch‑decode‑execute (F‑E) cycle efficiently and increases overall instruction throughput.

Classification of registers

General‑purpose registers

GPRs are grouped in a register file. The number of registers and the width of each register (8‑, 16‑, 32‑ or 64‑bit) are architectural decisions that affect:

• Instruction‑encoding size (more registers → more bits needed for register specifiers).
• Amount of data that can be processed in one operation.
• Flexibility of addressing modes.

Special‑purpose registers

These registers belong to the CPU’s control logic. They are rarely addressed directly by user programmes, but they are essential for correct sequencing of instructions.

Register‑transfer notation (RTN)

RTN expresses the movement of data between registers (or between a register and memory) in a concise symbolic form. It is used throughout the syllabus when describing the F‑E cycle.

• PC → MAR                    // place address of next instruction on the address bus
• Memory[MAR] → MDR → IR        // fetch instruction from memory
• PC ← PC + 1              // point to following instruction
• IR[op] → ALU             // decode operation
• R₁, R₂ → ALU → ACC       // execute arithmetic/logic using GPRs
• ACC → MDR → Memory[MAR]    // store result (if required)
• ALU → SR              // update condition flags

Fetch‑Decode‑Execute (F‑D‑E) cycle – step‑by‑step

1. Fetch address: PC → MAR
2. Fetch instruction: Memory[MAR] → MDR → IR
3. Increment PC: PC ← PC + 1
4. Decode: Control unit interprets the opcode in IR and determines which GPR(s) and/or SPR(s) are required.
5. Execute

   • Read operands from the indicated GPRs (or via MAR/MDR).
   • ALU performs the operation.
   • Result is written to a destination register (often ACC) and, for a store instruction, to MDR for a memory write.
   • Condition flags are updated in the Status Register.

Register‑based addressing modes

Registers are used in several addressing modes. The table shows each mode, a short RTN example and a brief explanation.

Impact of registers on instruction‑set design and performance

• Operand‑field count: The number of GPRs determines how many operand fields can be encoded in a single instruction. More GPRs usually mean larger instruction words.
• Encoding limits: Fixed‑length instruction sets (e.g., RISC) allocate a fixed number of bits for register specifiers, which caps the maximum number of GPRs.
• Pipelining and hazards

  • Registers supply the data needed at each pipeline stage, reducing memory traffic.
  • Data hazards arise when an instruction needs a result that has not yet been written back to a GPR. Forwarding or stall logic uses the register file to resolve these hazards.

• RISC vs. CISC

  • RISC architectures typically provide a large, uniform set of GPRs (e.g., 32 × 32‑bit) and rely heavily on register‑to‑register operations.
  • CISC processors may have fewer GPRs and more complex addressing modes that involve SPRs such as segment registers.

Register width and privilege levels

• Register width: Determines the maximum size of data that can be processed in one operation (8, 16, 32, 64 bits). Wider registers enable higher‑performance arithmetic and larger address spaces.
• Privileged vs. user registers

  • Some SPRs (e.g., status register, interrupt‑mask registers) are only accessible in privileged mode, protecting the operating system from accidental modification.
  • GPRs are generally available to user programmes, although a few may be reserved for system calls or for the operating system.

Registers in interrupt handling

When an interrupt occurs the CPU must preserve the current execution state so that it can resume later.

1. Current PC (and often SR) are automatically pushed onto a stack or saved in dedicated interrupt registers.
2. The PC is loaded with the address of the interrupt‑service routine (ISR) taken from an interrupt vector table.
3. After the ISR finishes, the saved PC (and SR if required) are restored, allowing normal execution to continue.

Key differences between GPRs and SPRs

Typical datapath for an arithmetic instruction (ACC‑based example)

IR ← Memory[PC]          // fetch
PC ← PC + 1              // point to next instruction
ACC ← ACC op R₁          // perform operation using a GPR
SR ← update_flags(ACC)   // set condition flags

Summary

• Registers are essential for rapid instruction execution.
• General‑purpose registers provide flexible storage for operands, addresses and intermediate results.
• Special‑purpose registers manage the internal control flow, memory interfacing and status reporting of the CPU.
• Understanding register‑transfer notation, addressing modes and the way registers influence instruction‑set design and pipeline performance is fundamental for analysing any processor architecture covered in the Cambridge AS & A‑Level Computer Science syllabus.