The Cambridge syllabus expects you to list and briefly explain the core functions of an OS. Use the short notes below when revising.
Translation software converts high‑level source code into a form the computer can execute. The table adds a concise side‑by‑side comparison of compilers and interpreters – a common exam topic.
| Software | What it does | Typical A‑Level use | Advantages | Disadvantages |
|---|---|---|---|---|
| Assembler | Translates symbolic assembly language to machine code (one‑to‑one mapping). | Micro‑controller projects, low‑level hardware control. | Fast, gives full hardware control. | Hard to write/maintain; no high‑level constructs. |
| Compiler | Translates an entire program to object code before execution. | Java, C, C++ projects. | Optimises code; execution is fast. | Long compilation time; errors appear only after compile. |
| Interpreter | Executes source code line‑by‑line, translating each statement on the fly. | Python, BASIC teaching environments. | Immediate feedback; easy debugging. | Slower execution; no separate executable. |
| Just‑In‑Time (JIT) Compiler | Combines interpretation and compilation; hot code sections are compiled at runtime. | Java Virtual Machine, .NET CLR. | Balances speed and flexibility. | Complex; occasional pause‑times. |
| Integrated Development Environment (IDE) | Provides editing, building, debugging and project‑management tools in one package. | Eclipse, Visual Studio, PyCharm. | Boosts productivity; visual debugging. | Resource‑heavy; learning curve. |
Logical (virtual) address – Address generated by a program.
Physical address – Actual location in RAM.
Address translation – Conversion performed by the Memory Management Unit (MMU).
Page – Fixed‑size block of virtual memory (e.g., 4 KB).
Frame – Fixed‑size block of physical memory, same size as a page.
Segment – Variable‑size logical unit (code, stack, heap, etc.).
Page table / Segment table – Data structures that map virtual pages/segments to physical frames.
Virtual memory gives each process the illusion of a large, contiguous address space, independent of the real RAM size. The MMU uses a page table (or segment table) to perform the translation.
Address‑translation formula (paging)
V = p × S + d
Physical address:
P = f × S + d
Assume a page size of 4 KB (2¹² bytes). A logical address 0x1234ABCD is split as:
0x1234A (upper 20 bits)0xBCD (lower 12 bits)If the page table maps 0x1234A → frame 0x5F2, the physical address becomes:
P = 0x5F2 × 0x1000 + 0xBCD = 0x5F2BCD
| Algorithm | How it works | Typical behaviour |
|---|---|---|
| FIFO (First‑In‑First‑Out) | Evicts the page that has been in memory the longest. | Simple; can suffer from Belady’s anomaly. |
| LRU (Least‑Recently‑Used) | Evicts the page not referenced for the longest time. | Close to optimal; needs hardware counters or approximations. |
| Clock (Second‑Chance) | Pages form a circular list; a use‑bit gives a second chance before eviction. | Efficient hardware implementation; approximates LRU. |
L = Bases + o provided o < Limits
The segment table supplies Bases and Limits. The resulting linear address L can then be paged if a hybrid scheme is used.
Assume segment 2 has Base = 0x4000 and Limit = 0x0A00. A logical address (2, 0x03F0) translates to linear address 0x4000 + 0x03F0 = 0x43F0. If the offset exceeded the limit, a protection fault would occur.
Most modern OSes use a hybrid approach: each segment is further divided into pages. This gives the logical organisation of segmentation together with the allocation efficiency of paging.

| Aspect | Paging | Segmentation | Hybrid (Paged Segmentation) |
|---|---|---|---|
| Unit size | Fixed (e.g., 4 KB) | Variable, defined by programmer | Segments variable; each segment split into fixed‑size pages |
| Fragmentation | Internal only | External possible | Internal (pages) + minimal external (segments) |
| Address‑translation steps | Virtual page → frame (page table) | Segment number → base address (segment table) | Segment → page table → page → frame (two tables) |
| Protection granularity | Per page (R/W/X bits) | Per segment (R/W/X bits) | Both segment‑level and page‑level protection |
| Typical use in modern OSes | Core memory manager (e.g., Windows, Linux) | Logical grouping in some micro‑kernels | Most 64‑bit OSes (x86‑64 uses segmentation for privilege, paging for memory) |
0111 1111 (+127) and 0000 0001 (+1) yields 1000 0000 (‑128) – a sign‑overflow.Given 192.168.10.0/24, a /26 subnet yields four subnets:
192.168.10.0‑63, 64‑127, 128‑191, 192‑255.
| Device | Key Component | Typical Use |
|---|---|---|
| Smartphone | ARM Cortex‑A78 CPU, LPDDR5 RAM | Multimedia, sensors, networking |
| IoT sensor node | Microcontroller (ATmega328P), EEPROM | Temperature monitoring, low‑power data logging |
math.h).0x12 0xA4 0xFF (answer: 0x0B).Use this worksheet to spot gaps quickly. Tick the box if the topic is covered, then add a short note on what needs to be added or improved.
| Syllabus Section | Covered? | Action if ❌ |
|---|---|---|
| 1 Information Representation (binary, BCD, ASCII/Unicode, overflow, two’s‑/one’s‑complement) | ☐ | Add overflow examples, ASCII ↔ Unicode table. |
| 2 Communication (LAN/WAN, topologies, OSI/TCP‑IP, IP addressing, subnetting, DNS) | ☐ | Insert OSI stack diagram, subnet‑mask calculation exercise. |
| 3 Hardware (RAM/ROM types, PROM/EPROM/EEPROM, buffers, embedded systems) | ☐ | Provide hardware‑in‑context table and sensor‑reading activity. |
| 4 Processor Fundamentals (Von Neumann, registers, ALU/CU, buses, clock, interrupts, F‑E cycle) | ☐ | Add fetch‑execute flowchart and quick‑fire register quiz. |
| 5 System Software (OS purposes, utilities, libraries, translators, IDE) | ☐ | Include side‑by‑side compiler vs interpreter table; mini‑IDE project suggestion. |
| 6 Security & Data Integrity (threats, firewalls, passwords, encryption basics, validation) | ☐ | Insert phishing case‑study and checksum generation task. |
| 7 Ethics & Ownership (professional ethics, copyright, licences, AI impact) | ☐ | Add code‑of‑ethics vignette and licence‑selection decision tree. |
| 8 Databases (file‑based limits, relational model, ER diagrams) | ☐ | Provide ER‑diagram example and relational‑schema conversion. |
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