Cambridge A-Level Computer Science 9618 – 3.1 Computers and Their Components
3.1 Computers and Their Components
Static RAM (SRAM) vs Dynamic RAM (DRAM)
Both SRAM and DRAM are types of volatile memory used as the main working storage in computers. Although they serve the same purpose—providing fast read/write access for the CPU—they differ fundamentally in construction, operation, performance, and cost.
Static RAM (SRAM)
Uses a flip‑flop circuit (typically 4–6 transistors) to store each bit.
Data is retained as long as power is supplied; no refresh required.
Fast access times (typically 10–20 ns).
Higher power consumption per bit because more transistors are active.
Low density – larger physical size per bit.
Commonly used for CPU caches (L1, L2, L3) and small high‑speed buffers.
Dynamic RAM (DRAM)
Stores each bit as charge on a tiny capacitor.
Capacitor leaks charge, so each cell must be refreshed periodically (every \$\approx 64\text{ ms}\$).
Higher density – a single transistor + capacitor per bit.
Slower access times (typically 50–100 ns) due to refresh overhead.
Lower power per bit when idle, but extra power for refresh cycles.
Used for main system memory (e.g., DDR4, DDR5 modules).
Direct Comparison
Feature
SRAM
DRAM
Cell Structure
4–6 transistors per bit (flip‑flop)
1 transistor + 1 capacitor per bit
Data Retention
Stable as long as power is on (no refresh)
Requires periodic refresh (≈ \$64\text{ ms}\$)
Access Time
\overline{10}–20 ns (fast)
\overline{50}–100 ns (slower)
Density
Low (large cell size)
High (compact cells)
Power Consumption
Higher static power per bit
Lower static power, but refresh power added
Cost per Bit
More expensive
Cheaper
Typical Use
CPU caches, register files, small buffers
Main system memory, video RAM (with modifications)
Key Points to Remember
SRAM’s flip‑flop design makes it fast but bulky and costly.
DRAM’s capacitor design enables high density but introduces the need for refresh cycles.
The choice between SRAM and DRAM is a trade‑off between speed, size, power, and cost.
In modern computers, both types coexist: SRAM for cache hierarchy, DRAM for main memory.
Suggested diagram: Cross‑section of an SRAM cell (flip‑flop) versus a DRAM cell (capacitor + transistor), showing the need for refresh in DRAM.