Cambridge A-Level Computer Science – 4.1 CPU Architecture
4.1 Central Processing Unit (CPU) Architecture
Learning Objective
Show understanding of how data are transferred between the various components of a computer system using the address bus, data bus and control bus.
1. Overview of CPU Architecture
The CPU is the “brain” of the computer. It consists of three main sub‑units:
Arithmetic Logic Unit (ALU) – performs arithmetic and logical operations.
Control Unit (CU) – generates control signals that direct the operation of the CPU and other components.
Registers – small, fast storage locations inside the CPU used for temporary data holding.
All of these sub‑units communicate with each other and with external components (memory, I/O devices) via three groups of parallel wires collectively called buses.
2. The Three Buses
Address Bus – carries the memory address of the location to be read from or written to.
Data Bus – carries the actual data being transferred.
Control Bus – carries timing and control signals such as read/write, interrupt, and clock.
3. Address Bus
The address bus is unidirectional: the CPU places an address on the bus, and memory or an I/O device decodes it.
If the address bus is \$n\$ bits wide, the CPU can address \$2^{n}\$ distinct locations. For example, a 16‑bit address bus can address \$2^{16}=65\,536\$ memory words.
Typical widths: 8, 16, 20, 32, 64 bits.
Higher width → larger addressable memory space.
4. Data Bus
The data bus is bidirectional; it can transfer data either from the CPU to memory/I‑O or from memory/I‑O to the CPU.
The width of the data bus determines the amount of data transferred in a single bus cycle:
8‑bit bus → 1 byte per cycle.
16‑bit bus → 2 bytes per cycle.
32‑bit bus → 4 bytes per cycle, etc.
Wider data buses improve throughput but increase hardware cost and complexity.
5. Control Bus
The control bus carries a set of signals that coordinate the activities of the CPU, memory and I/O devices. Key signals include:
Read (RD) – indicates that the CPU wants to read data from the addressed location.
Write (WR) – indicates that the CPU wants to write data to the addressed location.
Clock (CLK) – synchronises all operations.
Interrupt (INT) – signals the CPU that an external event requires attention.
Bus Enable (BE) – activates the data bus for a transfer.
6. Data Transfer Example – The Fetch‑Execute Cycle
Below is a step‑by‑step description of how the three buses work together during a single instruction fetch.
Program Counter (PC) value placed on the address bus. The CU asserts the Read signal on the control bus.
Memory decodes the address. The addressed memory word (the instruction) is placed on the data bus.
CPU reads the instruction. The data bus transfers the instruction into the Instruction Register (IR).
PC is incremented. The CU updates the PC for the next instruction.
Decode and Execute. Depending on the instruction, additional address and data bus cycles may follow, with appropriate Read or Write control signals.
7. Summary Table of Bus Characteristics
Bus
Direction
Primary Function
Typical Width (bits)
Key Control Signals
Address Bus
Unidirectional (CPU → Memory/I‑O)
Selects memory or I/O location
8, 16, 20, 32, 64
None (address lines only)
Data Bus
Bidirectional
Transfers actual data values
8, 16, 32, 64
Read (RD), Write (WR), Bus Enable (BE)
Control Bus
Bidirectional (varies per signal)
Coordinates timing and operation
Varies – typically a few lines
RD, WR, CLK, INT, BE, Reset, etc.
Suggested diagram: A block diagram showing the CPU connected to memory and I/O devices via the three buses (address, data, control). Label the direction of each bus and indicate typical signal lines on the control bus.
8. Key Points to Remember
The address bus determines the maximum addressable memory space.
The data bus width defines how much data can be moved per bus cycle.
The control bus carries timing and command signals that ensure orderly data transfer.
All three buses work together in every operation, from fetching an instruction to reading or writing data.