Show understanding of how data are transferred between various components of the computer system using the address bus, data bus and control bus

4.1 Central Processing Unit (CPU) – Architecture & Buses

Learning objective

Show understanding of how data are transferred between the various components of a computer system using the address bus, data bus and control bus.

1. Overview of the CPU

The CPU is the “brain” of the computer. It contains three functional units and a set of special‑purpose registers that cooperate during every instruction cycle.

• Arithmetic Logic Unit (ALU) – performs arithmetic and logical operations.
• Control Unit (CU) – generates the control‑signal patterns that coordinate the CPU, main memory and I/O devices.
• Registers – very fast storage inside the CPU. The Cambridge AS/A‑Level syllabus expects you to know the following registers:

Advanced note (A‑Level depth): Some processors also provide an Index Register (X), Stack Pointer (SP) and a Program Status Word (PSW). These are not required for AS but are useful when studying more complex instruction sets.

2. Von Neumann vs. Harvard architectures

Both models use the same three‑bus concept, but they differ in how memory is organised.

3. The three system buses

All communication between the CPU, main memory and I/O devices occurs via three parallel groups of wires collectively called buses.

3.1 Address bus

• Direction: Unidirectional – always CPU → memory/I‑O.
• Function: Carries the binary address of the location to be accessed.
• Width ↔ addressable space: An n‑bit address bus can address 2ⁿ distinct locations. For a byte‑addressable system this equals 2ⁿ bytes.

  • 20‑bit bus → 2²⁰ = 1 048 576 bytes ≈ 1 MiB.
  • 32‑bit bus → 2³² ≈ 4 GB.

• Typical widths: 8, 16, 20, 32, 64 bits.
• Application – memory‑mapped I/O: I/O devices are given addresses in the same space as RAM, so the same address bus is used to select an I/O register.

3.2 Data bus

• Direction: Bidirectional – data can travel CPU → memory/I‑O (write) or memory/I‑O → CPU (read).
• Function: Carries the actual data value being transferred.
• Width ↔ throughput: Number of bits transferred in one bus cycle (normally one CPU clock period).

  • 8‑bit bus → 1 byte per cycle.
  • 16‑bit bus → 2 bytes per cycle.
  • 32‑bit bus → 4 bytes per cycle.
  • 64‑bit bus → 8 bytes per cycle.

• Relation to clock speed: Theoretical maximum bandwidth = (clock frequency) × (data‑bus width). Real‑world rates are lower because of protocol overhead, wait states, etc.
• Limitations: Bus contention, need for multiplexing, cost/complexity of wider buses.

3.3 Control bus

• Direction: Individual lines have fixed direction (e.g., CPU → memory for WR, device → CPU for INT), but the whole bus is considered bidirectional.
• Function: Carries timing, command and status signals that synchronise the address and data buses.
• Key signals required by the Cambridge syllabus (exact symbols used in the exam):

3.4 How the control bus synchronises a transfer

1. CPU places the required address on the address bus.
2. CPU asserts RD (or WR) together with BE on the control bus.
3. Memory or I/O recognises the control signals, then either drives the data bus (read) or samples the data bus (write).
4. On the next rising edge of CLK the operation is considered complete; the control lines are de‑asserted.

4. Interrupt handling – role of the control bus

When an external device needs CPU attention it raises the INT line. The sequence is:

1. INT goes high while the CPU is in the middle of a fetch‑execute cycle.
2. The CU finishes the current micro‑operation, then asserts INT‑ACK to acknowledge the request.
3. The PC, MAR and other registers are saved (often onto a stack) and the PC is loaded with the address of the interrupt‑service routine (ISR).
4. After the ISR finishes, a RTI (return from interrupt) instruction restores the saved registers and the CPU resumes the interrupted program.

All of the above signalling occurs on the control bus; the address and data buses are used only when the ISR fetches its own instructions.

5. Bus arbitration – multiple bus masters

In simple single‑processor systems the CPU is the only master. In more advanced designs (e.g., DMA controllers, multi‑core CPUs) other devices may need temporary control of the address and data buses.

A typical arbitration scheme works as follows:

1. Device that wants the bus asserts BUS‑REQ.
2. The CPU (or an arbiter) evaluates the request. If the bus is free it asserts BUS‑GRANT to the requesting device.
3. The granted device becomes the master, drives the address and data buses, and de‑asserts BUS‑REQ when finished.
4. The CPU regains master status by de‑asserting BUS‑GRANT.

This mechanism prevents two masters from driving the same lines simultaneously, which would cause data corruption.

6. Memory‑mapped I/O – concrete example

Assume a simple system where the keyboard status register is mapped to address 0xFF00 and the data register (the key code) to 0xFF01.

1. CPU wants to read the status: MAR ← 0xFF00.
2. CPU asserts RD + BE.
3. The keyboard controller recognises the address, places the status byte on the data bus, and the CPU loads it into MDR.
4. If the status indicates a key is ready, the CPU repeats the process with 0xFF01 to obtain the actual key code.

Notice that the same RD and WR signals are used as for ordinary RAM accesses; the only difference is the address value.

7. Fetch‑execute cycle – micro‑operations (register‑transfer notation)

The table below shows the minimum sequence required to fetch one instruction. The notation follows the Cambridge specification: “←” denotes a transfer, “+” denotes arithmetic, and “+1” is a shorthand for “increment by one”.

Timing diagram (reference)

A typical two‑clock‑cycle diagram shows:

• First half‑cycle: address bus is stable; RD/WR asserted.
• Second half‑cycle: data bus becomes active for a read (driven by memory) or for a write (driven by CPU).
• CLK rising edge marks the end of the cycle.

8. RTN cheat‑sheet (quick reference)

9. Worked examples (AO2 – quantitative reasoning)

Example 1 – basic

A computer has a 20‑bit address bus and a 16‑bit data bus. The CPU runs at 1.5 GHz.

1. Maximum addressable memory: 2²⁰ = 1 048 576 bytes ≈ 1 MiB.
2. Data transferred per bus cycle: 16 bits = 2 bytes.
3. Theoretical maximum bandwidth: 1.5 GHz × 2 bytes = 3 GB s⁻¹.

Example 2 – challenging

A modern workstation uses a 64‑bit data bus and a 3 GHz clock. Assume the bus can transfer data on every clock edge (no wait states).

1. Maximum theoretical bandwidth: 3 GHz × 64 bits = 192 Gb s⁻¹ ≈ 24 GB s⁻¹.
2. Real‑world comment: In practice the achievable bandwidth is lower because of protocol overhead, cache latency, and the need for read‑modify‑write cycles. Typical measured values for a 3 GHz, 64‑bit system are around 15–18 GB s⁻¹.

10. Summary table of bus characteristics

11. Key points to remember

• The address‑bus width determines the maximum number of distinct memory locations (2ⁿ).
• The data‑bus width defines how many bits move per clock cycle; together with the CPU frequency it gives the theoretical bandwidth.
• The control bus carries the timing and command signals (RD, WR, BE, CLK, INT, etc.) that synchronise the address and data buses.
• During a fetch:

  1. PC → address bus (MAR receives it).
  2. RD + BE asserted.
  3. Memory places the instruction on the data bus; CPU loads it into MDR.
  4. IR ← MDR; PC ← PC + 1.

• Memory‑mapped I/O uses the same address and control signals as RAM; the only difference is the address range.
• Interrupts are signalled on the control bus (INT) and cause the CPU to suspend the normal fetch‑execute sequence, save the current state, execute an ISR, then resume.
• When more than one component can act as a bus master, BUS‑REQ / BUS‑GRANT arbitration prevents bus contention.