Understand how different ports provide connection to peripheral devices

Published by Patrick Mutisya · 14 days ago

Cambridge A-Level CS 9618 – 4.1 CPU Architecture

4.1 Central Processing Unit (CPU) Architecture

The CPU is the brain of a computer system. It executes instructions, performs arithmetic and logic operations, and controls the flow of data between the processor, memory and peripheral devices. In this section we focus on how the CPU connects to peripherals through various types of ports.

CPU Core and Control Unit

  • ALU (Arithmetic Logic Unit) – performs arithmetic and logical operations.

  • Control Unit (CU) – fetches, decodes and executes instructions, generates control signals.

  • Registers – small, fast storage locations used for immediate data and addresses.

Bus Architecture

The CPU communicates with other components via buses. A bus is a collection of wires that carry data, addresses and control signals.

  1. Address Bus – carries the memory or I/O address from the CPU to the bus.

  2. Data Bus – carries the actual data being read or written.

  3. Control Bus – carries control signals such as read/write, interrupt, and clock.

Peripheral Connection via Ports

Peripheral devices are connected to the CPU through ports. There are two main methods of port addressing:

  • Memory‑Mapped I/O (MMIO) – peripheral registers share the same address space as memory.

  • Port‑Mapped I/O (PMIO) – uses a separate address space dedicated to I/O ports.

In MMIO, the CPU treats peripheral registers as if they were memory locations. In PMIO, the CPU uses specific instructions (e.g., IN/OUT on x86) to read from or write to port addresses.

Common Port Types

Port TypeTypical UseData Transfer ModeSpeed (approx.)
Serial Port (UART)Keyboard, Modem, Serial consoleByte‑by‑byte, asynchronous115.2 kbit/s
Parallel Port (LPT)Printers, legacy devices8‑bit parallel, synchronous1–2 Mbit/s
USB (Universal Serial Bus)Keyboards, mice, storage, networkingPacket‑based, full/low/high speed12 Mbit/s (USB 1.1), 480 Mbit/s (USB 2.0)
PCIe (Peripheral Component Interconnect Express)Graphics cards, SSDs, network cardsHigh‑bandwidth, point‑to‑point2.5 Gbit/s per lane (PCIe 1.0), up to 32 Gbit/s (PCIe 4.0)
SPI (Serial Peripheral Interface)Microcontrollers, sensorsFull‑duplex, synchronousUp to 10 Mbit/s
I²C (Inter‑Integrated Circuit)Sensor interfaces, EEPROMsHalf‑duplex, synchronousUp to 400 kbit/s (Fast mode)

Addressing Example (Memory‑Mapped I/O)

Suppose a peripheral device has a base address of \$0x4000\$ and exposes four 8‑bit registers at offsets \$0x00\$, \$0x01\$, \$0x02\$, and \$0x03\$. The CPU can read the second register with the following address calculation:

\$\$

\text{Address} = \text{Base} + \text{Offset} = 0x4000 + 0x01 = 0x4001

\$\$

The CPU then performs a read operation on the data bus at address \$0x4001\$ to obtain the register value.

Interrupts and Port Communication

Peripherals often signal the CPU via interrupt lines. When an interrupt occurs, the CPU temporarily stops its current task, saves its state, and jumps to an interrupt service routine (ISR). The ISR typically reads or writes data through the appropriate port to acknowledge or process the event.

Key Takeaways

  • The CPU uses buses to exchange data, addresses and control signals.

  • Peripherals are accessed either through memory‑mapped or port‑mapped I/O.

  • Different port types support various data transfer modes and speeds.

  • Interrupts allow peripherals to asynchronously notify the CPU of events.

Suggested diagram: CPU bus architecture showing address, data and control buses connecting to memory and peripheral ports.