Show understanding of the purpose and roles of the Arithmetic and Logic Unit (ALU), Control Unit (CU) and system clock, Immediate Access Store (IAS)

4.1 Central Processing Unit (CPU) Architecture

Purpose of the CPU

The CPU is the brain of the computer. It fetches instructions from memory, decodes them, executes the required operations and stores results. Its operation is synchronised by a system clock.

Key Components

• Arithmetic and Logic Unit (ALU) – performs arithmetic (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR).
• Control Unit (CU) – generates control signals that direct data flow between the ALU, registers, memory and I/O devices.
• System Clock – provides a regular timing pulse that coordinates the activities of all CPU components.
• Immediate Access Store (IAS) – a small, fast memory (often called registers) that holds operands and intermediate results for the ALU.

Arithmetic and Logic Unit (ALU)

The ALU receives two operands from the IAS, performs the required operation, and returns the result to the IAS or to a destination register. Typical operations include:

• Arithmetic: \$A + B\$, \$A - B\$, \$A \times B\$, \$A \div B\$
• Logical: \$A \cdot B\$, \$A + B\$, \$\overline{A}\$, \$A \oplus B\$
• Shift/rotate: \$A \ll n\$, \$A \gg n\$

Control Unit (CU)

The CU interprets the instruction opcode and generates a sequence of control signals. Its main responsibilities are:

1. Fetch the next instruction from main memory.
2. Decode the opcode to determine the required operation.
3. Activate the appropriate data paths (e.g., select registers, enable ALU operation).
4. Manage program flow (branching, jumps, interrupts).

System Clock

The system clock produces a periodic waveform (often a square wave) with a frequency \$f{clk}\$. Each rising (or falling) edge of the clock triggers a new CPU cycle, ensuring that all components operate in lock‑step. The clock period \$T{clk}\$ is given by:

\$T{clk} = \frac{1}{f{clk}}\$

Immediate Access Store (IAS)

The IAS is a collection of registers that provide the fastest possible access to data. Typical registers include:

• Accumulator (ACC) – primary operand/result register for the ALU.
• General‑purpose registers (R0–R7) – hold temporary data and addresses.
• Program Counter (PC) – holds the address of the next instruction to fetch.
• Status Register (SR) – contains flags (Zero, Carry, Overflow, Sign) set by the ALU.

Interaction of Components – Example Cycle

Consider the instruction ADD R1, R2 (add contents of R2 to R1). The sequence is:

1. Fetch: CU signals memory to place the instruction at the address in PC onto the bus.
2. Decode: CU recognises the opcode for ADD and identifies source register R2 and destination register R1.
3. Read Operands: CU activates the register file to place R1 and R2 onto the ALU input lines.
4. Execute: ALU performs \$R1 + R2\$ and sets appropriate status flags.
5. Write Back: CU routes the ALU result back into R1.
6. Increment PC: CU increments PC for the next instruction, all actions synchronised by the clock.

Component Summary Table