Show understanding of the purpose and roles of the Arithmetic and Logic Unit (ALU), Control Unit (CU) and system clock, Immediate Access Store (IAS)

4.1 Central Processing Unit (CPU) Architecture

Purpose of the CPU

The CPU is the “brain” of the computer. It repeatedly performs the fetch‑decode‑execute‑write‑back cycle, moving instructions from memory, interpreting them, carrying out the required operations and storing the results. All activities are synchronised by a system clock.

Von Neumann Model & Stored‑Program Concept

• Both data and instructions are stored in the same main‑memory.
• The CPU treats an instruction exactly like any other piece of data: it fetches it from memory, decodes the opcode, and then executes it.
• This model underpins the fetch‑execute cycle and allows programs to be modified by other programs (e.g., loaders, compilers).

Registers – Immediate Access Store (IAS)

The IAS is the collection of registers that give the CPU its fastest access to data, addresses and control information.

Bus Architecture (Three‑Bus Model)

• Address bus – carries memory addresses from the CPU to RAM or I/O devices.
• Data bus – carries the actual data being read or written.
• Control bus – carries timing and control signals (Read/Write, Interrupt Acknowledge, Clock Enable, etc.).

Arithmetic and Logic Unit (ALU)

The ALU receives two operands from the IAS, performs the selected operation and returns the result to a register or memory location.

• Arithmetic operations: addition, subtraction, multiplication, integer division.
• Logical operations: AND, OR, NOT, XOR.
• Shift/rotate operations:

  • Logical shift left/right (fills with 0).
  • Arithmetic shift right (preserves sign bit).
  • Rotate left/right (bits wrap around).

• Bit‑manipulation: masking, setting, clearing and testing individual bits – a common requirement in assembly‑language programming.

Control Unit (CU)

1. Decodes the opcode in the IR and determines which registers, ALU operation and addressing mode are required.
2. Generates the exact sequence of control signals for each micro‑step of the fetch‑execute cycle.
3. Activates the appropriate paths on the address, data and control buses.
4. Manages program flow – sequential execution, branches, jumps and interrupt handling.
5. Coordinates timing with the system clock.

System Clock

A crystal‑controlled oscillator produces a regular square‑wave of frequency f_clk. The clock period is

\$T{clk}= \frac{1}{f{clk}}\$

Each rising (or falling) edge defines the start of a new micro‑step, ensuring that all CPU components operate in lock‑step.

Six‑step Fetch‑Execute Cycle (Micro‑steps)

1. Fetch instruction – CU asserts Read on the control bus, places the address from PC on the address bus, and loads the instruction into IR via MDR.
2. Increment PC – CU adds the instruction length (normally 1 word) to PC so it points to the next instruction.
3. Decode – CU examines the opcode in IR and selects the required ALU operation, registers and addressing mode.
4. Fetch operands – CU activates the register file (or memory) to place the required operands on the data bus and into the ALU input registers.
5. Execute – ALU performs the selected operation; status flags in SR are updated.
6. Write‑back – CU routes the ALU result to the destination register or memory location; any post‑processing (e.g., sign‑extension) is performed.

Interrupts – Purpose and Handling

Interrupts allow external devices to gain the CPU’s attention without polling.

1. An I/O device asserts an Interrupt Request (IRQ) on the control bus.
2. The CU finishes the current micro‑step, then saves the current PC (often on a hardware stack).
3. The PC is loaded with the address of the Interrupt Service Routine (ISR) taken from a fixed interrupt‑vector table.
4. The ISR executes, typically acknowledging the device and performing the required service.
5. At the end of the ISR, a RETI (return from interrupt) instruction restores the saved PC, allowing normal program flow to resume.

Performance Factors (Cambridge AO2)

• Clock speed – higher f_clk shortens each micro‑step.
• Instruction‑level parallelism – superscalar CPUs can issue several independent instructions per clock cycle.
• Pipelining – overlapping the six micro‑steps of successive instructions (fetch of instruction n+1 while instruction n is executing).
• Cache hierarchy – fast on‑chip memory (L1, L2, L3) reduces the time spent accessing main memory.
• Multiple cores – true parallelism by running independent instruction streams on separate processing units.

Peripheral Ports & I/O Controllers

Ports are the external “faces” of the computer; an I/O controller sits on the data and control buses and translates port‑level signals into the protocol used by the device.

Assembly Language – Relationship to the CPU

Each assembly instruction corresponds to a machine‑code word that contains an opcode (identifying the operation) and operand fields (register numbers, address offsets, etc.). During the decode micro‑step the CU extracts the opcode, selects the appropriate ALU operation, and determines which registers or memory locations are involved. Understanding this mapping is essential for answering AO1 (knowledge) and AO2 (application) questions.

Virtual Memory (Brief Overview)

At A‑Level, students should be able to state that virtual memory allows a program to use more address space than physically available by mapping logical addresses to physical frames via a page‑table. The mapping is performed by the Memory Management Unit (MMU), which works in concert with the CPU’s control logic.

Example: Execution of ADD R1, R2

1. Fetch – CU asserts Read, places PC on the address bus, and loads the ADD R1,R2 instruction into IR.
2. Increment PC – PC ← PC + 1.
3. Decode – CU recognises the ADD opcode, identifies source register R2 and destination register R1.
4. Read Operands – CU activates the register file; contents of R1 and R2 are placed on the data bus and into the ALU inputs.
5. Execute – ALU computes R1 + R2, updates Zero/Carry flags in SR.
6. Write‑back – CU routes the result back to R1.

Each step is triggered by a successive clock edge, illustrating the tight coupling between the system clock, CU, ALU and IAS.

Component Summary