Show understanding of how factors contribute to the performance of the computer system

Published by Patrick Mutisya · 14 days ago

Cambridge A-Level Computer Science 9618 – 4.1 CPU Architecture

4.1 Central Processing Unit (CPU) Architecture

Learning Objective

Show understanding of how various factors contribute to the overall performance of a computer system.

1. Core Components of a CPU

  • Control Unit (CU) – directs the operation of the processor.

  • Arithmetic Logic Unit (ALU) – performs arithmetic and logical operations.

  • Registers – small, fast storage locations inside the CPU.

  • Cache Memory – a small, high‑speed memory that stores frequently accessed data.

  • Clock Generator – provides timing signals that synchronise operations.

Suggested diagram: Block diagram of a CPU showing CU, ALU, registers, cache and clock.

2. The Instruction Cycle (Fetch–Decode–Execute)

  1. Fetch: Retrieve the next instruction from memory using the Program Counter (PC).

  2. Decode: Translate the binary instruction into control signals for the CU and ALU.

  3. Execute: Perform the operation (ALU computation, memory access, or branch).

  4. Write‑back (optional): Store the result in a register or memory location.

3. Quantifying CPU Performance

The fundamental performance equation is:

\$\text{CPU Time} = \frac{\text{Instruction Count} \times \text{CPI}}{\text{Clock Rate}}\$

where:

  • Instruction Count (IC) – total number of instructions executed for a program.

  • CPI – average cycles per instruction, dependent on instruction mix and architecture.

  • Clock Rate – frequency of the CPU clock (in Hz).

4. Factors Influencing Performance

FactorEffect on PerformanceTypical Mitigation Techniques
Clock SpeedHigher frequency reduces the denominator of the performance equation, decreasing CPU time.Advanced semiconductor processes, dynamic frequency scaling.
CPI (Cycles per Instruction)Lower CPI reduces the numerator, speeding up execution.Pipelining, superscalar execution, micro‑op fusion.
Instruction CountFewer instructions mean less work to be performed.Optimised compilers, use of complex instruction set (CISC) vs. reduced instruction set (RISC).
Cache HierarchyEffective caching reduces memory access latency, lowering CPI for memory‑bound instructions.Multi‑level caches, larger cache lines, write‑back policies.
PipeliningAllows overlapping of instruction stages, effectively decreasing CPI.Deep pipelines, hazard detection and forwarding.
Parallelism (Multiple Cores / SIMD)Enables simultaneous execution of independent instructions, reducing overall program time.Multi‑core designs, vector units, thread-level parallelism.
Branch PredictionAccurate prediction prevents pipeline stalls caused by control hazards.Dynamic predictors, hybrid schemes.

5. Example Calculation

Consider a program that executes 1.2 × 10⁹ instructions on a processor with a 2.5 GHz clock and an average CPI of 1.8.

\$\text{CPU Time} = \frac{1.2 \times 10^{9} \times 1.8}{2.5 \times 10^{9}} = \frac{2.16 \times 10^{9}}{2.5 \times 10^{9}} = 0.864\ \text{s}\$

If a cache optimisation reduces the average CPI to 1.4, the new execution time becomes:

\$\text{CPU Time}_{\text{new}} = \frac{1.2 \times 10^{9} \times 1.4}{2.5 \times 10^{9}} = 0.672\ \text{s}\$

This illustrates how a modest reduction in CPI can produce a noticeable performance gain.

6. Summary Checklist

  • Identify the three main stages of the instruction cycle.

  • Recall the CPU performance equation and the meaning of each term.

  • Explain how clock speed, CPI, instruction count, cache, pipelining and parallelism each affect overall speed.

  • Perform basic calculations to compare performance before and after an optimisation.