Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors

15 Processor Fundamentals, Parallel Processing & Virtual Machines

Learning Objectives

• Explain the concepts of ISA, RISC and CISC and their impact on processor design.
• Use the performance equation to analyse CPU time, CPI and clock‑rate.
• Describe classic pipeline stages, identify hazards and outline common mitigation techniques.
• Compare superscalar, multicore, SIMD and MIMD architectures.
• Understand the role of virtual machines (VMs) in ISA translation and software portability.
• Apply AO1–AO3 skills: recall facts, analyse performance, and design simple code fragments.

Key Terminology

Performance Equation

The fundamental relationship used in the syllabus is:

\$\text{CPU time} = \frac{\text{Instruction count} \times \text{CPI}}{\text{Clock rate}}\$

• Clock rate – measured in Hz (or GHz). The reciprocal gives the clock period (seconds per cycle).
• CPI – average cycles per instruction; may differ for instruction classes (e.g., load/store vs arithmetic).
• Instruction count – total number of machine instructions executed (including repeats due to loops).

RISC vs CISC – Comparative Overview

Advantages & Disadvantages (summary)

Classic 5‑Stage RISC Pipeline

| IF | ID | EX | MEM | WB |

1. IF – Instruction Fetch
2. ID – Decode & Register Fetch
3. EX – Execute / Address Calculation
4. MEM – Memory Access
5. WB – Write‑Back to Register

Typical Hazards

• Structural hazard – two instructions need the same hardware resource in the same cycle.
• Data hazard – an instruction depends on the result of a previous one.

  • RAW (Read‑After‑Write)
  • WAR (Write‑After‑Read)
  • WAW (Write‑After‑Write)

• Control hazard – caused by branches; mitigated by branch prediction, delay slots or pipeline flushing.

Hazard‑resolution techniques (AO2)

• Forwarding (bypassing) – routes ALU results directly to a later instruction’s EX stage.
• Stalling (pipeline bubbles) – inserts NOPs until the required data is ready.
• Branch prediction – hardware guesses the outcome; correct prediction avoids flushing.

Example – Data Hazard & Forwarding

ADD R1, R2, R3   // R1 = R2 + R3
SUB R4, R1, R5   // uses R1 produced by previous ADD

Without forwarding the SUB would have to wait one cycle. With forwarding the result from the EX stage of ADD is sent directly to the EX stage of SUB, eliminating the stall.

Beyond the Classic Pipeline

Superscalar Execution

• One core can issue multiple independent instructions per clock cycle.
• Requires several execution units (ALU, FP‑unit, load/store unit) and sophisticated scheduling logic.

Multicore Processors

• Two or more independent cores on the same die, each with its own pipeline.
• Overall speed‑up follows Amdahl’s Law:

  \$\text{Speed‑up}= \frac{1}{(1-P)+\frac{P}{N}}\$

  where P = parallel fraction, N = number of cores.

• Example: 70 % parallelisable code on 4 cores → speed‑up ≈ 2.1×.

SIMD & MIMD

Virtual Machines (VMs)

A VM provides a software layer that abstracts the underlying hardware ISA, enabling the same program to run on different physical processors.

Key Concepts

• Byte‑code – compact, platform‑independent instruction set (e.g., Java byte‑code, .NET CIL).
• Interpretation – each byte‑code instruction is fetched and executed directly by a software interpreter; simple but slower.
• Just‑In‑Time (JIT) compilation – translates hot byte‑code sections into native machine code (RISC or CISC) at runtime, achieving near‑native speeds.
• Stack‑based VM – operands are pushed onto an operand stack (e.g., Java Virtual Machine).
• Register‑based VM – uses virtual registers to reduce stack overhead (e.g., Dalvik, Lua).
• VMs enable platform independence – a crucial point for Paper 4 (programming) where the same source may be run on different architectures.

VM Execution Flow (simplified)

Assessment‑Focused Activities (AO1‑AO3)

1 Information Representation

• Binary, octal, hexadecimal, and their conversion methods.
• Signed numbers: two’s complement, sign‑magnitude, excess‑k.
• Floating‑point representation (IEEE 754 single & double precision) – sign, exponent, mantissa.
• Character encoding: ASCII, Unicode (UTF‑8/16).
• Data compression basics (lossless vs lossy) – relevance to storage and transmission.

2 Communication & Networks

• Network topologies: bus, star, ring, mesh.
• Transmission media: twisted pair, coaxial, fibre‑optic, wireless.
• OSI model – 7 layers and key functions of each layer.
• Common protocols: TCP/IP, HTTP, FTP, SMTP, DNS.
• Bandwidth, latency, throughput; calculation of transmission time:

  \$\text{Transmission time}= \frac{\text{File size}}{\text{Bandwidth}} + \text{Latency}\$

3 Hardware Fundamentals

• Logic gates, Boolean algebra, truth tables.
• Combinational circuits: adders, multiplexers, encoders.
• Sequential circuits: flip‑flops, registers, counters, state machines.
• Memory hierarchy – registers, cache (L1‑L3), main memory (RAM), secondary storage.
• Input/Output devices and interfaces (USB, HDMI, PCIe).

4 Processor Fundamentals (RISC/CISC) – see section above

5 System Software

• Operating system functions: process management, memory management, file system, device drivers, security.
• System calls – interface between user programmes and OS.
• Utility software: compilers, assemblers, linkers, debuggers, interpreters.
• Virtualisation basics – hypervisors (Type 1 vs Type 2).

6 Security

• Confidentiality, integrity, availability (CIA triad).
• Symmetric encryption (DES, AES) – block ciphers, key length, modes of operation.
• Asymmetric encryption (RSA, ECC) – public/private key pair, digital signatures.
• Hash functions (MD5, SHA‑256) – purpose and properties.
• Authentication mechanisms: passwords, biometrics, two‑factor authentication.
• Common threats: malware, phishing, denial‑of‑service, insider attacks.

7 Ethics & Legal Issues

• Intellectual property: copyright, patents, licences (GPL, MIT, proprietary).
• Privacy legislation: GDPR, Data Protection Act.
• Professional codes of conduct (e.g., BCS, ACM).
• Impact of computing on society – digital divide, environmental concerns.

8 Databases

• Relational model – tables, primary keys, foreign keys.
• SQL basics: SELECT, INSERT, UPDATE, DELETE, JOIN types.
• Normalization – 1NF, 2NF, 3NF, BCNF.
• Indexing – B‑tree, hash indexes; effect on query performance.
• Transaction concepts: ACID properties, concurrency control (locks, deadlock).

9 Algorithms

• Algorithm design – problem definition, input, output, steps.
• Complexity analysis – Big‑O notation, best/average/worst case.
• Common algorithms: linear search, binary search, sorting (bubble, insertion, selection, merge, quicksort).
• Recursive algorithms – base case, recursive step, stack usage.
• Graph algorithms – breadth‑first search (BFS), depth‑first search (DFS), Dijkstra’s shortest path.

10 Data Types & Structures

• Primitive types – integer, floating‑point, character, Boolean.
• Composite types – arrays (single‑ and multi‑dimensional), records/structures, strings.
• Abstract data types – stacks, queues, linked lists, trees, hash tables.
• Dynamic data structures – allocation, deallocation, memory leaks.

11 Programming (Paper 4)

• Algorithm design using pseudocode and flowcharts.
• Control structures – sequence, selection (if/else, switch), iteration (for, while, do‑while).
• Procedures/functions – parameters (pass‑by‑value/reference), recursion.
• Exception handling – try/catch, error propagation.
• Testing – unit testing, black‑box vs white‑box, test data selection.

12 Software Development Life‑Cycle (SDLC)

• Stages: requirements, analysis, design, implementation, testing, deployment, maintenance.
• Methodologies: waterfall, agile (Scrum, Kanban), rapid application development.
• Documentation – specifications, user manuals, maintenance logs.
• Version control basics – commit, branch, merge.

13 User‑Defined Data Types (A‑Level)

• Creating new types with typedef (C) or class/struct (Java, C++).
• Encapsulation – private data, public methods.
• Operator overloading (where supported) – example of vector addition.

14 File Organisation

• Sequential vs random access files.
• File structures – fixed‑length records, variable‑length records, indexed files.
• Operations: open, read, write, close, seek.
• File handling in Java (FileReader/Writer, Buffered streams) and Python (open, read, write).

15 Floating‑Point Representation (A‑Level)

• IEEE 754 single (32‑bit) and double (64‑bit) format.
• Normalised vs denormalised numbers, special values (NaN, ±∞).
• Rounding modes – round‑to‑nearest, truncation.
• Common pitfalls: overflow, underflow, loss of precision.

16 Network Protocols (A‑Level)

• TCP vs UDP – reliability, connection‑oriented vs connection‑less.
• HTTP/HTTPS – request methods, status codes, secure sockets.
• SMTP & POP/IMAP – email transmission and retrieval.
• Routing protocols – RIP, OSPF, BGP (basic concepts).

17 Parallel Processing (Expanded – see section above)

• ILP techniques – pipelining, superscalar, out‑of‑order execution.
• TL‑P – multicore, multithreading, SIMD vector units.
• Amdahl’s Law and Gustafson’s Law – limits of speed‑up.
• Examples of parallel programming models: OpenMP (shared memory), MPI (distributed memory).

18 Boolean Algebra & Logic Design (A‑Level)

• Fundamental theorems – De Morgan’s, consensus, absorption.
• Simplification using Karnaugh maps (K‑maps) – grouping of 1’s/0’s.
• Design of combinational circuits – minimised SOP/POS forms.
• Sequential circuit design – state‑transition tables, state diagrams, implementation with flip‑flops.

19 Advanced Operating System Topics (A‑Level)

• Process scheduling algorithms – FCFS, SJF, Round‑Robin, priority, multilevel feedback.
• Memory management – paging, segmentation, virtual memory, page replacement policies (FIFO, LRU, optimal).
• Deadlock – conditions, detection, prevention, avoidance (Banker’s algorithm).
• File system concepts – FAT, NTFS, ext4, journaling.

20 Translation Software, Encryption & AI (A‑Level)

Translation Software

• Compilers – lexical analysis, parsing, optimisation, code generation.
• Assemblers – translating symbolic assembly to machine code.
• Interpreters – direct execution of high‑level code (e.g., Python).
• Linkers & loaders – combining object files, resolving symbols, relocation.

Encryption (re‑visit)

• Public‑key infrastructure (PKI) – certificates, certificate authorities.
• Digital signatures – generation and verification process.
• Secure hash algorithms – SHA‑256, SHA‑3, collision resistance.

Artificial Intelligence (A‑Level)

• Search algorithms – uninformed (BFS, DFS, uniform‑cost) and informed (A*, greedy).
• Knowledge representation – semantic networks, frames, production rules.
• Machine learning basics – supervised vs unsupervised, simple linear regression example.
• Ethical considerations – bias, privacy, impact on employment.

Quick Revision Checklist (AO1)

• Define ISA, RISC, CISC, micro‑code.
• State the performance equation and explain each term.
• List the five classic pipeline stages and the three hazard types.
• Give two advantages of SIMD over scalar execution.
• Describe how a Java VM achieves platform independence.
• Recall the four layers of the OSI model.
• Write the binary representation of the decimal number 45.
• Identify the main difference between TCP and UDP.
• Explain what a deadlock is and name one condition that must hold for a deadlock to occur.
• State the purpose of a hash function in security.

Further Practice (AO2 & AO3)

1. Calculate the CPI for a mixed‑instruction program where 50 % are arithmetic (CPI = 1) and 50 % are memory accesses (CPI = 3). The program runs 5 × 10⁵ instructions on a 1.5 GHz CPU. (Show all work.)
2. Design a simple flowchart for a program that reads a list of numbers, stores them in an array, and then outputs the maximum value. Include decision symbols for end‑of‑input detection.
3. Write a short Java method that uses a for loop to compute the factorial of an integer n. Then, show how the same algorithm would be expressed in pseudo‑assembly for a RISC processor (use LOAD, MUL, ADD, BRANCH).
4. Given a 4‑bit Karnaugh map with minterms m(1,3,5,7), minimise the Boolean expression and draw the resulting logic circuit.
5. Using Amdahl’s Law, determine the maximum theoretical speed‑up if 95 % of a program can be parallelised and an unlimited number of cores are available.

Summary

Understanding the trade‑offs between RISC and CISC, the mechanics of pipelining, and the ways modern CPUs achieve parallelism is central to analysing processor performance (AO2). Virtual machines extend this knowledge by showing how software can be insulated from hardware differences, a key point for programming and software development (AO3). By integrating these concepts with the broader AS and A‑Level topics – data representation, networking, security, databases, algorithms, and AI – students gain a holistic view of computer science as required by the Cambridge International syllabus.