Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors

Published by Patrick Mutisya · 14 days ago

Cambridge A-Level Computer Science 9618 – 15.1 Processors, Parallel Processing and \cdot irtual Machines

15.1 Processors, Parallel Processing and \cdot irtual Machines

Objective

Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors.

Key Concepts

  • Instruction Set Architecture (ISA) – the set of operations a processor can execute.

  • RISC – a design philosophy that uses a small, highly optimized set of simple instructions.

  • CISC – a design philosophy that provides a large set of complex instructions, often capable of performing multi‑step operations in a single instruction.

  • Clock Cycle, CPI and CPU Time – fundamental performance metrics.

Performance Equation

The relationship between instruction count, cycles per instruction (CPI) and clock rate is expressed as:

\$\text{CPU time} = \frac{\text{Instruction count} \times \text{CPI}}{\text{Clock rate}}\$

RISC vs CISC – Comparative Overview

AspectRISCCISC
Instruction lengthFixed (usually 32 bits)Variable (1–15 bytes)
Number of instructionsSmall (≈ 50–100)Large (≈ 200–500)
Typical CPILow (≈ 1–2)Higher (≈ 3–5)
Execution modelLoad‑store architecture – memory accessed only by explicit load/store instructionsMemory‑to‑memory – many instructions operate directly on memory operands
Pipeline friendlinessHighly amenable – simple, uniform instructions allow deep pipelinesMore complex – variable length and side effects can cause pipeline stalls
Hardware complexitySimpler control unit, larger register fileMore complex control logic, micro‑code ROM
Typical examplesARM, MIPS, RISC‑VIntel x86, AMD64, VAX

Advantages of RISC

  1. Predictable execution time – easier to calculate CPI.

  2. Efficient pipelining – reduces instruction latency.

  3. Simpler hardware – lower power consumption, useful for embedded systems.

  4. Compiler optimisation – compilers can generate efficient code because instruction behaviour is uniform.

Disadvantages of RISC

  1. Higher instruction count for complex operations, potentially increasing memory traffic.

  2. Requires larger register files, which can increase die area.

  3. Older software ecosystems may lack native RISC support.

Advantages of CISC

  1. Fewer instructions needed for complex tasks – can reduce program size.

  2. Rich instruction set simplifies assembly programming and legacy code compatibility.

  3. Integrated addressing modes reduce the need for multiple load/store instructions.

Disadvantages of CISC

  1. Variable‑length instructions complicate decoding and pipelining.

  2. Higher hardware complexity – more transistors, higher power consumption.

  3. Micro‑code layers can add latency to instruction execution.

Impact on Parallel Processing

Both RISC and CISC processors can implement superscalar and multi‑core designs, but the ease of parallel execution differs:

  • RISC – uniform instruction length and simple decoding make it easier to issue multiple instructions per cycle.

  • CISC – modern CISC CPUs (e.g., Intel Core series) translate complex instructions into micro‑operations internally, effectively creating a RISC‑like pipeline.

Virtual Machines and ISA Translation

Virtual machines (VMs) abstract the underlying hardware ISA, allowing software written for one ISA to run on another. Two common approaches are:

  • Interpretation – each \cdot M instruction is fetched and executed directly, incurring overhead.

  • Just‑In‑Time (JIT) compilation – VM bytecode is dynamically translated to the host ISA (RISC or CISC), achieving near‑native performance.

Suggested diagram: Comparison of a simple RISC pipeline (fetch → decode → execute → memory → write‑back) versus a CISC micro‑operation pipeline (fetch → decode → micro‑code ROM → multiple execution stages).

Summary

Understanding the trade‑offs between RISC and CISC is essential for analysing processor performance, especially when considering pipelining, parallel execution, and the role of virtual machines. While RISC emphasises simplicity and speed, CISC offers rich instruction semantics that can reduce code size. Modern processors often blend both philosophies, using micro‑code to break complex CISC instructions into RISC‑like micro‑operations.