Show understanding of a flip-flop (SR, JK)

15.2 Boolean Algebra and Logic Circuits – Flip‑Flops

Learning Objective

Demonstrate a clear understanding of the operation, characteristic equations and practical use of the SR and JK flip‑flops.

1. Introduction to Flip‑Flops

A flip‑flop is a bistable multivibrator that stores one bit of information. It has two stable states, usually represented as Q = 0 and Q = 1, and changes state only on a triggering edge of a clock signal.

2. SR (Set‑Reset) Flip‑Flop

The SR flip‑flop has two inputs, S (Set) and R (Reset), and two outputs, Q and \$\overline{Q}\$. The basic behaviour is summarised in the truth table below.

The characteristic equation of the SR latch (when built from NAND gates) is:

\$Q_{next}=S+\overline{R}\,Q\$

Key points:

• The SR latch is level‑sensitive; its output follows the inputs while the enable (clock) is active.
• The forbidden state (S = R = 1) must be avoided in practical designs.
• It can be built from NOR or NAND gates; the polarity of inputs changes accordingly.

3. JK Flip‑Flop

The JK flip‑flop resolves the invalid condition of the SR latch by toggling the output when both inputs are high. It has inputs J, K and a clock (or edge‑trigger) input.

Characteristic equation (edge‑triggered JK flip‑flop):

\$Q_{next}=J\overline{Q}+ \overline{K}Q\$

Excitation (or transition) table – shows which J and K values are required to obtain a desired transition from the present state Q to the next state \$Q^{+}\$:

Where “X” denotes a “don’t‑care” condition.

4. Comparison of SR and JK Flip‑Flops

1. Invalid State – SR has an illegal input combination (S = R = 1); JK eliminates this by defining a toggle operation.
2. Edge Sensitivity – JK flip‑flops are normally edge‑triggered, making them suitable for synchronous designs; SR latches are level‑sensitive.
3. Use in Counters – JK toggling makes it ideal for binary counters, while SR would require additional gating.
4. Complexity – JK requires more gates, but the added functionality outweighs the cost in most sequential circuits.

5. Practical Applications

• Memory elements in registers and RAM cells.
• Frequency division (JK toggle used as a divide‑by‑2 counter).
• State machines – storing the current state of a finite‑state machine.
• Debounce circuits – SR latch can hold a stable output while a mechanical switch settles.

6. Summary

The SR flip‑flop provides the basic set‑reset functionality but suffers from an undefined input condition. The JK flip‑flop extends this concept, offering a well‑defined toggle operation that removes the illegal state, making it the preferred choice for most synchronous sequential circuits. Understanding the truth tables, characteristic equations and excitation tables is essential for designing reliable digital systems.