Describe the stages of the Fetch-Execute (F-E) cycle

1 Information Representation

1.1 Number Bases & Binary Arithmetic

• Binary (base‑2), octal (base‑8) and hexadecimal (base‑16) are the three bases used in computer systems.
• Conversions:

  • Binary → Decimal: sum of 2ⁿ bits.
  • Decimal → Binary: repeated division by 2.
  • Hex ↔ Binary: each hex digit = 4 bits.

• Two’s‑complement representation for signed integers:

  • Positive numbers: same as unsigned.
  • Negative numbers: invert bits and add 1.
  • Range for *n*‑bit word: –2ⁿ⁻¹ … 2ⁿ⁻¹ – 1.

1.2 Character & Text Encodings

• ASCII – 7‑bit code (0‑127) for English characters.
• Extended ASCII – 8‑bit (0‑255) adds symbols and accented letters.
• Unicode – 16‑bit (UTF‑16) or variable‑length (UTF‑8) to represent world‑wide characters.

1.3 Data Types & Representations

1.4 Multimedia Representation

• Images – bitmap (pixel matrix) vs. vector (geometric primitives). Example: a 640 × 480 24‑bit colour bitmap uses 640 × 480 × 3 = 921 600 bytes ≈ 0.9 MB.
• Sound – sampled at a rate (e.g., 44.1 kHz) with a bit depth (e.g., 16 bits). A 5‑second mono CD‑quality audio file: 44 100 samples × 5 s × 2 bytes ≈ 441 kB.
• Compression

  • Lossless (e.g., Run‑Length Encoding, Huffman coding) – original data can be perfectly reconstructed.
  • Lossy (e.g., JPEG for images, MP3 for audio) – some information is discarded for higher compression ratios.

2 Communication & Networking

2.1 Basic Concepts

• Network – a collection of devices (nodes) linked by communication channels.
• Topology – physical or logical arrangement (star, bus, ring, mesh).
• Protocol – a set of rules that governs data exchange (e.g., TCP, HTTP).

2.2 The OSI & TCP/IP Models

2.3 IP Addressing & DNS

• IPv4 – 32‑bit address written as four octets (e.g., 192.168.1.10).
• Subnet mask separates network and host portions.
• Domain Name System (DNS) translates human‑readable domain names to IP addresses.

2.4 Client‑Server vs. Peer‑to‑Peer

• Client‑Server – centralised resources (web server, database server).
• Peer‑to‑Peer (P2P) – each node can act as both client and server (e.g., file‑sharing).

2.5 Cloud Computing (AS Level focus)

• Delivery of services (IaaS, PaaS, SaaS) over the Internet.
• Advantages: scalability, cost‑effectiveness; disadvantages: dependence on network, security concerns.

2.6 Practical Activity

Capture a simple HTTP request with Wireshark, identify the source/destination IP addresses, protocol (TCP), and the request line (“GET /index.html HTTP/1.1”). Discuss how the OSI layers are involved.

3 Hardware Components & Logic Circuits

3.1 Memory Hierarchy

• Registers – fastest, located inside the CPU (few bytes).
• Cache – small, fast SRAM (L1, L2, L3) sits between registers and main memory.
• Main Memory – DRAM, volatile, accessed in nanoseconds.
• Secondary Storage – magnetic disks, SSDs, optical media – slower but non‑volatile.

3.2 Logic Gates & Simple Circuits

Lab idea: build a half‑adder using two XOR gates and an AND gate; extend to a full‑adder and discuss how adders are combined to form an ALU.

3.3 Peripheral Devices & I/O Ports

• Input devices – keyboard, mouse, sensors.
• Output devices – monitor, printer, actuators.
• Storage devices – HDD, SSD, USB flash.
• I/O ports – parallel (e.g., printer), serial (UART, USB), and specialised buses (PCIe, USB‑C).

4 Processor Fundamentals

4.1 CPU Architecture Overview

• Implements the Von Neumann stored‑program model: program instructions and data share the same memory.
• Core components: Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Instruction Register (IR), Accumulator/General‑purpose registers, Status/Condition Register (SR), Arithmetic‑Logic Unit (ALU), Control Unit.
• Three bus systems:

  • Address bus – carries addresses from PC/MAR to memory/I/O.
  • Data bus – carries data between memory, MDR and registers.
  • Control bus – carries read/write, interrupt, clock, and reset signals.

4.2 Fetch‑Execute (F‑E) Cycle – Detailed Stages

1. Fetch (Instruction Fetch)

   • PC → MAR (address placed on the address bus).
   • Read signal asserted on the control bus.
   • Instruction word travels on the data bus → MDR → IR.
   • PC is incremented (or later altered by a branch).

2. Decode (Instruction Decode)

   • Control unit examines the opcode in IR.
   • Micro‑control signals are generated for the required functional units.
   • Addressing mode is resolved (immediate, direct, indirect, indexed/relative).

3. Execute (Operation)

   • ALU performs the operation specified by the opcode (add, AND, shift, compare, etc.).
   • For load/store, the effective address calculated here is sent to MAR.
   • Condition‑code flags in SR are updated as required.

4. Write‑back (Store)

   • Result from the ALU or memory is written to the destination register (ACC, Rn) or back to memory.
   • For a store instruction: MDR → data bus → memory (address from MAR).
   • For a branch/jump, PC is overwritten with the target address computed during Execute.

Timing Diagram (simplified)

Time →   |---Fetch---|---Decode---|---Execute---|---Write‑back---|
PC       | Addr      |            |             |                |
MAR      | Addr      |            |             |                |
MDR      | Instr     |            |             | Result/Data    |
IR       | Instr     | Instr      |             |                |
ALU Op   |           |            | Op Code     |                |
SR Flags |           |            | Updated     |                |

4.3 Registers – Micro‑operations in the Cycle

4.4 Clock, Performance Factors & Cache

• CPU clock (MHz or GHz) defines the duration of a single machine cycle.
• Performance‑enhancing factors:

  • Wider address and data buses → more bits per transfer.
  • Pipeline depth – overlapping stages to increase instruction throughput.
  • Cache hierarchy (L1, L2, L3) – reduces average memory‑access time, shortening the fetch phase.
  • Instruction‑set design – RISC (simple, fixed‑length) vs. CISC (complex, variable‑length).

• Typical cache latency: L1 ≈ 1 cycle, L2 ≈ 4–10 cycles, L3 ≈ 10–30 cycles; main memory ≈ 100 cycles.

4.5 Interrupt Handling

1. CPU finishes the current micro‑operation.
2. Current PC and status register are saved (often on a stack).
3. PC is loaded with the address of the Interrupt Service Routine (ISR) from an interrupt vector table.
4. ISR executes; on return, the saved PC and SR are restored and normal execution resumes.

Interrupts enable multitasking, I/O handling and many security mechanisms.

4.6 Pipelining (Extended Concept)

Modern CPUs split the logical F‑E cycle into hardware stages (Fetch, Decode, Execute, Memory, Write‑back). Multiple instructions occupy different stages simultaneously, increasing instruction throughput while preserving the logical order for each instruction.

4.7 RISC vs. CISC – Comparative Table

4.8 Parallelism – SISD, SIMD, MIMD

• SISD – Single Instruction, Single Data (classic sequential processor).
• SIMD – Single Instruction, Multiple Data (vector processors, GPU shaders).
• MIMD – Multiple Instruction, Multiple Data (multicore CPUs, clusters).

Understanding these models prepares students for the A‑Level extension on parallel processing and virtual machines.

5 Assembly Language – Connecting Machine Code to Human‑Readable Form

5.1 Machine Code ↔ Assembly

• Each assembly instruction corresponds to one (or a small fixed number of) machine‑code words.
• The assembler translates symbolic mnemonics into binary opcodes and resolves addresses.

5.2 Two‑Pass Assembler

1. Pass 1 – Scan source, build symbol table (labels → addresses), calculate instruction lengths.
2. Pass 2 – Generate machine code, substitute symbolic addresses with numeric values from the table.

5.3 Common Addressing Modes (with one‑line examples)

5.4 Sample Mini‑Program (adds two numbers stored at 2000h and 2004h)

LDM   2000          ; Load first operand into ACC
ADD   2004          ; ACC ← ACC + M[2004]
STM   2008          ; Store result at 2008
HLT                 ; Halt the CPU

The F‑E cycle is performed four times – once for each instruction.

6 Bit Manipulation

• Logical shifts – move bits left/right, inserting zeros. Useful for multiplication/division by powers of two.
• Arithmetic shifts – preserve the sign bit when shifting right (signed division).
• Masking – AND a value with a bit‑mask to isolate or clear particular bits.
• Set / Clear – OR with a mask to set bits; AND with the complement of a mask to clear bits.

Example: clear bits 0‑3 of register R1

LDM   R1            ; Load R1 into ACC
AND   #0xFFF0       ; Mask with 1111 1111 1111 0000
STM   R1            ; Store back to R1

7 Operating Systems – The Software Layer that Controls the CPU

• Provides resource‑management: memory allocation, process scheduling, file handling, I/O control, and security.
• Context switching – saves current PC, registers and SR (often on a stack), loads the state of another process, then resumes execution. This is a controlled use of the interrupt mechanism.
• Manages privilege levels (user vs. kernel mode) to restrict direct access to privileged instructions and I/O ports, enhancing system security.

8 Language Translators – From Source Code to Machine Instructions

Regardless of the translator, the final step is the same: the CPU repeatedly performs the Fetch‑Decode‑Execute‑Write‑back cycle on the generated machine instructions.

9 Security, Data Integrity & Validation

• Security – protecting data from unauthorised access or modification.
• Privacy – ensuring personal data is not disclosed without consent.
• Integrity – guaranteeing that data is accurate and uncorrupted.

CPU‑Level Safeguards

• Privilege levels (user/kernel) prevent execution of privileged instructions by user programs.
• Interrupt masking and control‑register flags (e.g., IF – Interrupt‑Enable) limit when external events can affect execution.
• Parity bits, checksums and error‑detecting codes are generated by the ALU during data‑transfer operations.

Software‑Level Validation

• Input checking, authentication, and authorisation complement hardware mechanisms.
• Secure coding practices (e.g., avoiding buffer overflows) are essential for maintaining overall system security.

10 Ethics, Ownership & Professional Responsibility

• Respect intellectual property – adhere to software licences, cite sources, avoid plagiarism.
• Consider environmental impact – high‑frequency CPUs consume significant power; energy‑efficient design is a professional duty.
• Assess societal effects – embedded systems in safety‑critical devices (medical, automotive) require rigorous testing and ethical awareness.
• Follow professional codes of conduct (e.g., BCS Code of Conduct) – honesty, competence, and duty to protect user data.

11 Key Points to Remember

• The Fetch‑Execute cycle is the fundamental loop that turns binary instructions into actions.
• Each stage consists of several micro‑operations involving PC, MAR, MDR, IR, ACC, and SR.
• Understanding the registers and bus connections is essential for debugging assembly programs and for designing simple CPUs.
• Modern CPUs accelerate the logical cycle with pipelining, caches, wide buses, and parallelism, but the logical order of operations remains unchanged.
• Interrupts, privilege levels, and OS scheduling are built on the basic F‑E mechanism and provide the foundation for multitasking, security, and resource management.
• Assembly language, addressing modes, and bit‑manipulation instructions are direct manifestations of the underlying hardware actions described in the cycle.
• Data representation, networking, and broader hardware concepts are integral parts of the Cambridge AS/A‑Level Computer Science syllabus and must be mastered alongside processor fundamentals.