Cambridge A-Level Computer Science – 4.1 CPU Architecture: Fetch‑Execute Cycle
4.1 Central Processing Unit (CPU) Architecture
Objective
Describe the stages of the Fetch‑Execute (F‑E) cycle and explain the role of the main registers involved.
Overview of the Fetch‑Execute Cycle
The CPU repeatedly performs a series of operations known as the Fetch‑Execute cycle. Each iteration processes one machine instruction, moving data between memory and the processor and performing the required computation.
Stages of the Cycle
Fetch – Retrieve the next instruction from memory.
Decode – Interpret the opcode and identify required operands.
Execute – Perform the operation indicated by the opcode.
Store/Write‑back – Write results back to registers or memory.
Detailed Description of Each Stage
1. Fetch
The CPU uses the Program Counter (PC) to locate the next instruction.
The PC holds the address of the instruction to be fetched.
The address on the PC is placed on the address bus and sent to main memory.
Memory returns the instruction word, which is placed in the Instruction Register (IR).
After fetching, the PC is typically incremented: \$\text{PC} \leftarrow \text{PC} + 1\$ (or by the instruction length).
2. Decode
The control unit examines the opcode in the IR to determine what operation is required.
Control signals are generated to select the appropriate functional units.
If the instruction requires operands, the addressing mode is resolved (e.g., register, immediate, direct, indirect).
3. Execute
The selected arithmetic‑logic unit (ALU) or other functional unit carries out the operation.
For arithmetic/logic instructions, the ALU receives its operands from the register file or memory.
For branch instructions, the ALU may compute a new address for the PC.
Condition codes (Zero, Carry, Sign, Overflow) may be updated.
4. Store / Write‑back
The result of the execution stage is written back to its destination.
If the result is to be stored in a register, it is written to the register file.
If the result must be written to memory, the address is placed on the address bus and the data on the data bus.
For branch or jump instructions, the PC is updated with the target address.
Register Summary
Register
Purpose
Typical Size
Program Counter (PC)
Holds address of next instruction to fetch
32‑ or 64‑bit
Instruction Register (IR)
Stores the currently fetched instruction
Width of instruction word (e.g., 32 bits)
Memory Address Register (MAR)
Holds address for memory read/write operations
Same as address bus width
Memory Data Register (MDR)
Temporarily stores data transferred to/from memory
Same as data bus width
Accumulator (ACC) / General‑purpose registers
Hold operands and results for ALU operations
32‑ or 64‑bit
Status/Condition Register (SR)
Contains flags (Zero, Carry, Sign, Overflow)
Typically 8‑16 bits
Typical Timing Diagram (simplified)
The following sequence shows the logical order of control signals during one complete F‑E cycle.
Time → |---Fetch---|---Decode---|---Execute---|---Store---|
PC | Addr | | | |
MAR | Addr | | | |
MDR | Data | | | Data |
IR | Instr | Instr | | |
ALU Op | | | Op Code | |
Suggested diagram: Block diagram of a CPU showing the datapath (PC, MAR, MDR, IR, ALU, registers) with arrows indicating the flow of data during each stage of the Fetch‑Execute cycle.
Key Points to Remember
The F‑E cycle is the fundamental operation that allows a CPU to execute programs sequentially.
Each stage may involve multiple micro‑operations that are coordinated by the control unit.
Modern CPUs use pipelining, allowing several instructions to be in different stages simultaneously, but the logical order of stages remains the same.
Understanding the role of each register helps in debugging assembly programs and in designing simple CPUs.