Show understanding of the importance/use of pipelining and registers in RISC processors

15.1 Processors, Parallel Processing and \cdot irtual Machines

Objective: Understanding the importance and use of pipelining and registers in RISC processors

RISC (Reduced Instruction Set Computer) architectures are designed around a small, highly optimized set of instructions that can be executed in a single clock cycle. Two key features that enable this performance are pipelining and the extensive use of registers.

Pipelining in RISC Processors

Pipelining allows several instructions to be processed simultaneously by dividing the execution of each instruction into distinct stages. Each stage works on a different instruction during the same clock cycle.

The classic 5‑stage pipeline can be visualised as:

Key advantages of pipelining:

• Increases instruction throughput without raising the clock frequency.
• Allows a RISC processor to achieve high performance with a simple control unit.
• Facilitates deterministic timing, which is valuable for real‑time systems.

However, hazards can disrupt smooth operation:

1. Structural hazards – when hardware resources are insufficient for concurrent stages.
2. Data hazards – when an instruction depends on the result of a previous one still in the pipeline.
3. Control hazards – caused by branch instructions that change the program flow.

RISC designs mitigate these hazards through techniques such as:

• Forwarding (also called bypassing) to resolve data hazards.
• Branch prediction and delay slots to reduce control hazards.
• Duplicating functional units to avoid structural hazards.

Registers in RISC Processors

RISC architectures rely heavily on a large register file. The philosophy is “load/store”: only load and store instructions access memory; all other operations use registers.

Benefits of a rich register set:

• Reduces the frequency of costly memory accesses, improving average instruction time.
• Enables simple, fixed‑length instruction encoding, which speeds up decoding.
• Supports efficient implementation of pipelining because most data is already in fast, on‑chip storage.

Example of a typical RISC instruction format (MIPS‑like):

\$\$

\text{opcode}{6}\;|\;\text{rs}{5}\;|\;\text{rt}{5}\;|\;\text{rd}{5}\;|\;\text{shamt}{5}\;|\;\text{funct}{6}

\$\$

All fields are extracted directly from the instruction word, allowing the decode stage to route operands to the appropriate registers in a single clock cycle.

Interaction Between Pipelining and Registers

Because each pipeline stage reads from and writes to the register file, the register file must support simultaneous read and write operations. Typical implementations provide:

• Two read ports – allowing the EX stage to fetch two source operands.
• One write port – enabling the WB stage to store the result.

Consider the following sequence of RISC instructions:

add \$t0, \$t1, \$t2   # \$t0 = \$t1 + \$t2
sub \$t3, \$t0, \$t4   # \$t3 = \$t0 - \$t4
and \$t5, \$t3, \$t6   # \$t5 = \$t3 & \$t6

Without forwarding, the second instruction would have to wait until the first instruction reaches the WB stage. With forwarding, the result of add can be supplied directly from the EX/MEM pipeline register to the EX stage of the sub instruction, eliminating a stall.

Summary

• Pipelining breaks instruction execution into stages, increasing throughput.
• Registers provide fast, on‑chip storage, minimizing memory accesses.
• The combination of a deep pipeline and a large register file is a hallmark of RISC design, delivering high performance with relatively simple hardware.

Key Points for Examination

1. Explain why RISC processors favour a load/store architecture.
2. Describe the five stages of a classic RISC pipeline and the role of registers in each stage.
3. Identify and give examples of the three types of pipeline hazards.
4. Discuss how forwarding and branch delay slots mitigate hazards.
5. State the advantages of having multiple read ports in the register file.