Understand how different ports provide connection to peripheral devices

4.1 Central Processing Unit (CPU) Architecture

1. Von Neumann Model & Stored‑Program Concept

The Von Neumann architecture uses a single shared memory that holds both the program instructions and the data on which those instructions operate. The CPU fetches each instruction sequentially from this memory, decodes it, and then executes it – the essence of the stored‑program idea that underpins all modern computers.

2. CPU Core Components

• Arithmetic Logic Unit (ALU) – performs arithmetic (add, subtract, multiply, divide) and logical (AND, OR, NOT, XOR) operations.
• Control Unit (CU) – generates the control signals that orchestrate the fetch‑decode‑execute cycle and manage data movement on the buses.
• Registers
  • General‑purpose registers – typically R0‑R7 (or R0‑R15 on larger CPUs). Used for temporary data, intermediate results and address calculations.
  • Special‑purpose registers
    • PC – Program Counter: holds the address of the next instruction to be fetched.
    • IR – Instruction Register: holds the current instruction while it is being decoded.
    • ACC – Accumulator: primary operand/result register for the ALU (used in many simple CPUs).
    • MAR – Memory Address Register: places the address on the address bus.
    • MDR – Memory Data Register: holds data being transferred on the data bus.
    • IX – Index Register: used for indexed addressing modes.
    • Status/Flag Register: contains condition flags such as Zero, Carry, Overflow, Sign, etc.
• Immediate Access Store (IAS) / Cache – a small, very fast memory located on or very close to the CPU. Modern terminology is CPU cache. It stores the most recently used instructions or data, reducing the average access time (cache hit vs. miss).

3. System Clock & Timing

• The system clock generates a regular series of pulses called clock cycles.
• Clock frequency is expressed in hertz (e.g., 3 GHz = 3 × 10⁹ cycles s⁻¹). A 3 GHz CPU can perform up to three billion basic operations per second, although most instructions require more than one cycle.
• Each step of the fetch‑execute cycle (fetch, decode, execute, write‑back) is synchronised to one or more clock cycles.

4. Bus Architecture

The CPU communicates with memory and peripheral devices via three families of buses. Their width directly influences performance.

5. Fetch‑Execute Cycle (F‑E Cycle)

1. Fetch – PC places the address on the address bus; a read signal is asserted; the instruction is placed on the data bus and loaded into the IR.
2. Decode – CU interprets the opcode in the IR, determines required operands and the type of operation.
3. Execute – ALU carries out the operation, or CU initiates a memory/I/O transfer using the MAR/MDR.
4. Write‑Back / Update PC – Result is stored in a register or memory; PC is incremented (or altered by a branch/jump).

6. I/O Addressing: Ports

Peripheral devices are accessed by the CPU through ports**. The Cambridge syllabus recognises two distinct addressing schemes:

Register 0 : 0x4000
Register 1 : 0x4001
Register 2 : 0x4002
Register 3 : 0x4003