Cambridge Syllabus Notes

4.1 Central Processing Unit (CPU) Architecture

Objective – Show understanding of the purpose of interrupts

1. Quick overview of a CPU (Von Neumann model)

The CPU, main memory and I/O share a common system bus. Instructions and data occupy the same memory space (Von Neumann architecture).
Core components:
- Arithmetic‑Logic Unit (ALU) – performs arithmetic and logical operations.
- Control Unit (CU) – generates control signals that direct data movement and operation sequencing.
- Registers – small, fast storage locations inside the CPU (see §2).
- System clock – synchronises all internal operations.
Typical instruction processing follows the fetch‑decode‑execute‑write‑back cycle (see Fig. 1).

2. Registers and buses (required for 4.1)

Register	Purpose
Program Counter (PC)	Holds the address of the next instruction to fetch.
Memory Address Register (MAR)	Provides the address for a memory read or write.
Memory Data Register (MDR)	Temporarily stores data read from or to be written to memory.
Accumulator (ACC)	Primary operand/result register for the ALU.
Index Register (IX)	Used for address calculation (e.g., array indexing).
Status/Flag Register	Contains condition flags (Zero, Carry, Overflow, Interrupt Enable, etc.).

The three main buses that connect the CPU to memory and I/O are:

Address bus – carries memory or I/O addresses (unidirectional).
Data bus – carries the actual data being transferred (bidirectional).
Control bus – carries timing and control signals (Read/Write, Interrupt Request, Acknowledge, etc.).

3. The fetch‑execute cycle (illustrative flow)

Fig. 1 – Simplified fetch‑decode‑execute‑write‑back cycle (PC → MAR → MDR → ALU → ACC → PC).

4. Process scheduling (syllabus requirement for 4.1)

Process states – New, Ready, Running, Blocked (or Waiting), Terminated.
Ready queue – Holds processes that are waiting for the CPU.
Scheduler – Selects the next Ready process according to a scheduling algorithm (e.g., round‑robin, priority).
Interrupts are the mechanism by which the CPU can leave the Running state (e.g., timer interrupt) and return to the scheduler.

5. Purpose of interrupts

An interrupt is a signal that temporarily suspends the normal sequential execution of a program so that the CPU can service an event that requires immediate attention. After the interrupt service routine (ISR) finishes, the CPU restores the saved state and continues the original program.

Why interrupts are needed (syllabus points)

Responsiveness – React quickly to time‑critical events (key press, timer expiry).
Efficient use of CPU time – Removes the need for constant polling of devices.
Multitasking support – Allows the operating system to pre‑empt one process and run another.
Resource management – Handles I/O completion, error conditions and hardware failures.
Priority handling – More urgent interrupts can be serviced before less urgent ones.
Masking – Critical sections of code can temporarily disable (mask) lower‑priority interrupts.

6. Types of interrupts

Type	Source	Typical use
Hardware interrupt	External devices (keyboard, mouse, network card, disk controller)	Notify CPU that data is ready or a device needs service.
Software interrupt (trap)	Program instruction (e.g., `INT` on x86, `syscall` on ARM)	Request operating‑system services such as file I/O.
Timer interrupt	Internal timer circuit	Implement time slicing for pre‑emptive multitasking.
Exception (fault)	CPU detects an illegal operation (divide by zero, page fault, invalid opcode)	Transfer control to an error‑handling routine.

7. How an interrupt is handled (step‑by‑step)

Interrupt request (IRQ) raised – A device asserts its interrupt line on the control bus.
CPU acknowledges – At the end of the current instruction the CPU checks the Interrupt Enable flag.
Priority arbitration – If several IRQs are pending, the interrupt controller selects the highest‑priority request.
Save context – PC, status register (including the Interrupt Enable flag) and, if required, general‑purpose registers are pushed onto the stack.
Fetch interrupt vector – The CPU uses the interrupt number to index an interrupt vector table (IVT) and loads the address of the corresponding ISR.
Jump to ISR – Control is transferred to the ISR address.
Execute ISR – Typical actions: read/write device registers, acknowledge the device, set/clear flags.
Restore context – The saved PC, status register and any registers are popped from the stack.
Resume original program – Execution continues with the instruction that was interrupted.

Example – keyboard interrupt service routine (pseudo‑assembly)

INTERRUPT_VECTOR 0x09        ; keyboard IRQ vector
ISR_KEYBOARD:
    PUSH   AX                ; save registers used by ISR
    IN     AL, 0x60          ; read scan code from keyboard port
    CALL   PROCESS_KEY      ; store the code in a buffer
    POP    AX                ; restore registers
    IRET                     ; return from interrupt (restores PC & flags)

8. Performance impact of interrupts

Aspect	Effect of interrupts
CPU utilisation	Higher utilisation because the CPU works only when there is useful work, not while busy‑waiting.
Latency	Interrupt latency = time from IRQ assertion to start of ISR; depends on pipeline depth and masking.
Throughput	Generally increased, but excessive interrupt frequency can cause an “interrupt storm” and degrade throughput.
Overhead	Saving/restoring context and vector lookup add a few µs to each interrupt; this overhead is accounted for in real‑time designs.

9. Bit‑manipulation and interrupt flags (4.3 Bit manipulation)

Interrupt Enable (IE) flag – usually bit 0 of the status register; IE = 1 allows IRQs, IE = 0 masks them.
Mask registers (e.g., IMR on x86) use a bit mask to enable/disable individual device lines.
Logical shifts – defined in the syllabus as:
- LSL #n, R – logical shift left (fills with 0s).
- LSR #n, R – logical shift right (fills with 0s).
- ASL #n, R – arithmetic shift left (same as LSL).
- ASR #n, R – arithmetic shift right (preserves sign bit).
Example: LSL #3, R0 ; R0 = R0 << 3 turns binary 0000 1010₂ into 0101 0000₂.

Common mask operations (binary AND/OR):

        ; Enable all interrupts
        OR  STATUS, #0x01

        ; Disable interrupts (critical section)
        AND STATUS, #0xFE

10. Relevance to assembly language (4.2 Assembly language)

Relationship to machine code – Each assembly instruction corresponds to one or more machine‑code words; the assembler translates symbolic mnemonics into binary op‑codes.
Two‑pass assembler – Required by the syllabus:
1. Pass 1 scans the source, builds a symbol table (labels → addresses) and calculates instruction lengths.
2. Pass 2 generates the actual object code using the symbol table.
Addressing modes – Immediate, Direct, Indirect, Register, Indexed (used for arrays).

Sample two‑pass trace (simple program that adds two numbers and stores the result):

        ; ---------- Source (Pass 1) ----------
        START:   LOAD   R1, NUM1      ; R1 ← NUM1
                ADD    R1, NUM2      ; R1 ← R1 + NUM2
                STORE  R1, RESULT    ; RESULT ← R1
                HALT
        NUM1:    .WORD  0x0014
        NUM2:    .WORD  0x000A
        RESULT:  .WORD  0x0000

        ; ---------- Symbol table (Pass 1) ----------
        START   = 0x0000
        NUM1    = 0x000C
        NUM2    = 0x000E
        RESULT  = 0x0010

        ; ---------- Object code (Pass 2) ----------
        0x0000:  01 01 0C          ; LOAD  R1, [0x000C]
        0x0003:  03 01 0E          ; ADD   R1, [0x000E]
        0x0006:  02 01 10          ; STORE R1, [0x0010]
        0x0009:  FF                ; HALT
        0x000C:  14 00             ; NUM1 = 20
        0x000E:  0A 00             ; NUM2 = 10
        0x0010:  00 00             ; RESULT (initially 0)

Key instructions for interrupt handling (illustrated in the ISR example):
- PUSH/POP – save/restore registers.
- IN/OUT – port‑I/O.
- CLI/STI – clear/set the interrupt flag.
- IRET – return from interrupt (restores PC & flags).

11. Advanced processor concepts (A‑Level extensions)

Concept	Definition	Typical example
RISC vs. CISC	RISC uses many simple, fixed‑length instructions that are easy to pipeline; CISC packs more work into fewer, variable‑length instructions.	RISC – ARM v8, MIPS; CISC – Intel x86‑64, AMD 64.
Pipelining	Overlaps the fetch, decode, execute and write‑back stages so that several instructions are in different stages simultaneously.	5‑stage pipeline in a typical MIPS processor; hazards are resolved with stalls or forwarding.
Parallel processing (multi‑core)	Two or more independent CPU cores share the same memory system and interrupt controller; each core has its own local mask and may have a private vector table.	Quad‑core Intel Core i5 – each core can handle separate IRQs, coordinated by an APIC.
Virtual machines & hypervisors	Software layers that emulate a complete hardware platform; virtual devices generate “virtual interrupts” that the hypervisor maps to physical IRQs.	VMware ESXi delivering virtual PCI‑e interrupts to a guest OS.

12. Key points to remember

An interrupt temporarily suspends the current instruction stream and forces the CPU to execute an ISR.
The CPU must save the execution context (PC, status flags, registers) before servicing the interrupt.
Interrupt vectors locate the appropriate ISR; priority logic decides which IRQ is handled first.
Masking (disabling) interrupts protects critical sections of code.
Bit‑mask operations and shift instructions are used to enable, disable or prioritise individual interrupt lines.
Efficient interrupt handling improves responsiveness, reduces wasted CPU cycles, and enables pre‑emptive multitasking and real‑time behaviour.

Suggested diagram: Flowchart of the normal fetch‑decode‑execute cycle with a branch that diverts to the interrupt‑service routine when an IRQ is detected; include a side‑box showing the interrupt‑vector lookup and context‑save/restore steps.

Show understanding of the purpose of interrupts

4.1 Central Processing Unit (CPU) Architecture