Show understanding of the four basic computer architectures

15.1 Processors, Parallel Processing and Virtual Machines

Learning objective

Show understanding of the four basic computer architectures and the related concepts required by the Cambridge International AS & A Level Computer Science (9618) syllabus.

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Quick‑reference box – AS‑level foundations (for completeness)

These concise points give a rapid overview of the AS‑level topics that underpin the A‑level material covered later.

• Data representation: binary, hexadecimal, BCD, two’s complement, IEEE‑754 floating‑point, file‑organisation methods (sequential, random, indexed, hashing).
• Communication & Internet technologies: OSI model, TCP/IP stack, common protocols (HTTP, FTP, SMTP, DNS), packet structure.
• Hardware basics: CPU, ALU, registers, cache, main memory, I/O devices, bus structures.
• System software: operating‑system purposes, process & thread management, virtual memory, compilation pipeline.
• Security & ethics: symmetric vs. asymmetric encryption, SSL/TLS handshake, digital certificates, ethical considerations.
• Algorithms & data structures: linear & binary search, insertion & bubble sort, time‑ and space‑complexity analysis.
• Programming concepts: procedural, object‑oriented, functional paradigms; recursion; exception handling.

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1. Flynn’s Taxonomy – The Four Basic Architectures

Flynn classifies computer architectures by the number of concurrent instruction streams and data streams they can handle.

Architecture	Instruction streams	Data streams	Typical examples
SISD	1	1	Early single‑core CPUs (e.g., Intel 8086), most microcontrollers
SIMD	1	Multiple	GPU vector units, SIMD extensions such as SSE, AVX, NEON
MISD	Multiple	1	Fault‑tolerant pipelines, some specialised signal‑processing hardware (rare in practice)
MIMD	Multiple	Multiple	Multi‑core CPUs, clusters, distributed systems

Key characteristics

• SISD – one instruction operates on one datum at a time; no built‑in parallelism.
• SIMD – a single instruction is applied simultaneously to many data items; ideal for data‑parallel tasks such as image or signal processing.
• MISD – several instructions act on the same data stream; mainly theoretical, used in specialised fault‑tolerant designs.
• MIMD – independent processors execute different instructions on different data; supports task‑parallelism and forms the basis of modern multi‑core and distributed systems.

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2. RISC vs CISC Instruction Sets

Understanding the two dominant design philosophies helps explain why some architectures are easier to pipeline than others.

Aspect	RISC (Reduced Instruction Set Computing)	CISC (Complex Instruction Set Computing)
Instruction length	Fixed (usually 32 bits)	Variable (1–15 bytes)
Number of instructions	Few, simple (≈ 50‑100)	Many, complex (≈ 200‑500)
Typical operations per instruction	One simple operation (load, add, branch)	Multiple micro‑operations (e.g., string copy)
Pipeline friendliness	Highly amenable – regular format reduces decode time and hazards.	Harder – variable length and complex decoding can cause stalls.
Examples	ARM, RISC‑V, MIPS	x86, IBM System/360

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3. Pipelining & the Register File

A pipeline breaks the execution of an instruction into several stages that can operate concurrently, increasing instruction throughput.

• Typical 5‑stage pipeline: Fetch → Decode → Execute → Memory access → Write‑back.
• Hazards:
  • Structural – two instructions need the same hardware resource.
  • Data – a later instruction depends on the result of an earlier one.
  • Control – a branch changes the program flow.
• Registers act as a fast buffer between stages. A larger register file reduces the need to access slower main memory, which in turn lowers pipeline stalls.
• RISC advantage: Fixed‑length, single‑operation instructions make the decode stage simple, keeping the pipeline full with minimal stalls.
• CISC challenge: Variable‑length instructions and complex addressing modes can cause decode bottlenecks; modern CISC CPUs (e.g., x86) mitigate this by internally translating complex instructions into RISC‑like micro‑ops.

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4. Massively‑Parallel Computers

These systems contain thousands to millions of processing elements and rely heavily on SIMD‑style execution.

• GPU‑based compute clusters – e.g., NVIDIA DGX stations or cloud GPU farms. Thousands of small cores, wide SIMD lanes, very high memory bandwidth.
• IBM Blue Gene/Q – a supercomputer with 16‑core nodes; each core supports SIMD operations and is designed for energy‑efficient large‑scale parallelism.
• Key architectural traits:
  • Very high core count (often >10⁴ cores).
  • Predominantly SIMD execution within each node.
  • Hierarchical memory (fast on‑chip SRAM, high‑bandwidth DRAM).
  • Network‑on‑chip or high‑speed interconnects for distributed communication.

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5. Parallel‑Processing Models

1. Shared‑Memory Parallelism – multiple processors access a single address space. Common in MIMD multi‑core CPUs. Synchronisation is achieved with locks, semaphores, atomic instructions, or higher‑level constructs such as OpenMP.
2. Distributed‑Memory Parallelism – each processor has its own private memory; communication occurs via explicit message passing (e.g., MPI). Typical for clusters and massively‑parallel systems.

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6. Virtual Machines (VMs)

A virtual machine provides an abstract execution environment that isolates software from the underlying hardware.

• System VMs – emulate an entire physical computer, allowing several guest operating systems to run concurrently (e.g., VMware Workstation, VirtualBox).
• Process VMs – provide a runtime environment for a single program; they translate platform‑independent bytecode into native instructions at execution time (e.g., Java Virtual Machine, .NET Common Language Runtime).

Benefits of virtualisation

• Isolation of workloads – faults or security breaches in one VM do not affect others.
• Dynamic resource allocation – CPU, memory and storage can be re‑assigned without rebooting.
• Platform independence – the same bytecode runs on any hardware that hosts the appropriate VM.

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7. Additional A‑Level Topics Required by the Syllabus

7.1 Data Representation

• Binary, hexadecimal and BCD encodings.
• Two’s complement for signed integers.
• IEEE‑754 single‑ and double‑precision floating‑point format.
• File‑organisation methods: sequential, random (direct), indexed, and hashing.

7.2 Communication & Internet Technologies

• OSI model (7 layers) and the simplified TCP/IP model (4 layers).
• Key protocols and their purposes:
  • HTTP/HTTPS – web communication.
  • FTP – file transfer.
  • SMTP/POP3/IMAP – email.
  • DNS – domain name resolution.
• Simple packet diagram showing header fields (source/destination IP, source/destination port, protocol, checksum).

7.3 System Software

• Operating‑system functions: process scheduling, memory management (paging, segmentation, TLB), I/O handling, file‑system management, security & protection.
• Process management: creation, termination, context switching, inter‑process communication.
• Compilation pipeline: lexical analysis → syntax analysis → semantic analysis → optimisation → code generation → linking.

7.4 Security

• Symmetric encryption (AES, DES) – same key for encryption and decryption.
• Asymmetric encryption (RSA, ECC) – public/private key pair.
• SSL/TLS handshake – exchange of certificates, establishment of a shared secret, encrypted data transfer.
• Digital certificates – X.509 structure, role of Certificate Authorities.

7.5 Artificial Intelligence

• Search algorithms:
  • Uninformed: breadth‑first, depth‑first, uniform‑cost.
  • Informed: A*, Dijkstra’s algorithm.
• Machine‑learning categories:
  • Supervised learning – labelled training data.
  • Unsupervised learning – clustering, dimensionality reduction.
  • Reinforcement learning – agents, rewards, policy optimisation.
• Simple neural‑network diagram – input layer → hidden layer(s) → output layer, with weighted connections.

7.6 Computational Thinking & Problem‑Solving

Algorithm	Time complexity (worst case)	Space complexity	Typical use‑case
Linear search	O(n)	O(1)	Unordered lists
Binary search	O(log n)	O(1)	Sorted arrays
Insertion sort	O(n²)	O(1)	Small or nearly‑sorted datasets
Bubble sort	O(n²)	O(1)	Educational examples

7.7 Further Programming Concepts

• Programming paradigms:
  • Procedural – sequence of commands (e.g., C).
  • Object‑oriented – classes, objects, inheritance (e.g., Java, Python).
  • Functional – pure functions, immutability (e.g., Haskell, Lisp).
• Recursion – a function calling itself; base case and recursive step (example: factorial, binary‑tree traversal).
• Exception handling – try‑catch‑finally blocks to manage runtime errors gracefully.

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8. Cross‑topic link: Architecture ↔ Operating Systems

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9. Performance considerations (re‑examined)

Factor	SISD	SIMD	MIMD
Clock speed	Directly proportional to instruction throughput.	Clock speed plus vector width affect per‑lane performance.	Important, but overall throughput scales with core count.
Vector width / core count	Not applicable.	Wider SIMD lanes (e.g., 256‑bit AVX2, 512‑bit AVX‑512) increase data processed per cycle.	More cores = more independent instruction streams.
Memory bandwidth	Moderate demand – one stream at a time.	High demand; many data elements fetched simultaneously.	High demand across all cores; contention can become a bottleneck.
Scalability	Limited – adding transistors yields diminishing returns.	Scales with vector length and number of SIMD units (e.g., multiple GPU SMs).	Scales with core count and inter‑node communication efficiency.
Power efficiency	Generally lower per operation.	Very high for data‑parallel workloads because many operations share control logic.	Varies; modern CPUs balance performance and power using dynamic frequency scaling.

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10. Suggested diagram

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Summary

The four basic architectures—SISD, SIMD, MISD and MIMD—form the conceptual foundation for modern processor design. RISC and CISC philosophies explain why some CPUs are easier to pipeline, while pipelining and a rich register file are essential for high instruction throughput. Massively‑parallel computers extend SIMD ideas to thousands of cores, enabling today’s supercomputers and GPU clusters. Parallel‑processing models (shared vs. distributed memory) and virtual machines illustrate how software exploits these hardware capabilities, and they demonstrate the close relationship between architecture and operating‑system concepts such as scheduling, virtual memory, and security. The additional A‑level sections on data representation, networking, system software, security, AI, algorithm analysis, and programming paradigms complete the coverage required by the Cambridge International AS & A Level Computer Science syllabus.