| Unit | Syllabus Sections | Key Topics |
|---|---|---|
| AS Level | 1‑12 |
|
| A Level | 13‑20 |
|
Each unit supports the three Assessment Objectives (AO):
Integer formats store whole numbers only. Real‑world applications—scientific calculations, graphics, finance—require:
Floating‑point notation satisfies these needs by separating a significand (the “mantissa”) from an exponent, analogous to scientific notation in decimal.
| Field | Bits | Bias | Purpose |
|---|---|---|---|
| Sign (s) | 1 | — | 0 = positive, 1 = negative |
| Exponent (e) | 8 | 127 | Stores exponent + bias; all‑zero and all‑one patterns are reserved. |
| Fraction / Mantissa (f) | 23 | — | Fractional part of the significand; an implicit leading 1 is assumed for normalised numbers. |
The numeric value of a normalised pattern is
\[ V = (-1)^{s}\times (1.f)_{2}\times 2^{\,e-127} \]e = 0 and f = 0 → +0 (s = 0) or –0 (s = 1).e = 0 and f ≠ 0 → exponent = –126, no implicit leading 1 (value = (–1)ˢ × 0.f × 2⁻¹²⁶).e = 255 and f = 0 → +∞ (s = 0) or –∞ (s = 1).e = 255 and f ≠ 0 → signalling or quiet NaN.s | e | f.e from binary to decimal, then subtract the bias (127) to obtain the true exponent E.1 to the fraction bits: 1.f.1.f as a sum of powers of 2:
\[
1.f = 1 + \sum_{i=1}^{23} \frac{f_i}{2^{i}}
\]
0 10000001 10100000000000000000000
10000001₂ = 129₁₀ → E = 129 − 127 = 2.101000… → 1.f = 1.101₂.1.101₂ = 1 + 1/2 + 0/4 + 1/8 = 1.625.1.f × 2ᴱ where 1 ≤ 1.f < 2.
e = E + 127; write e as an 8‑bit binary number.1.f and fill the 23‑bit mantissa (pad with zeros if fewer bits).s | e | f gives the 32‑bit pattern.If more than 23 fraction bits are required, round to the nearest even value (the default IEEE 754 rounding mode). Other modes (toward 0, toward +∞, toward –∞) may be required for specialised applications.
Convert -0.15625 to IEEE 754 single‑precision.
0.15625:
0.00101₂.
0.00101₂ = 1.01₂ × 2⁻³ → E = –3.e = –3 + 127 = 124 = 01111100₂.01 → pad to 23 bits:
01000000000000000000000.
1 01111100 01000000000000000000000
FUNCTION floatToIEEE754(x):
IF x = 0:
RETURN "0 00000000 00000000000000000000000"
ENDIF
sign ← 0 IF x >= 0 ELSE 1
a ← ABS(x)
// 1. Convert integer part to binary
intPart ← FLOOR(a)
intBin ← binaryString(intPart) // e.g. 13 → "1101"
// 2. Convert fractional part to binary (up to 30 bits for safety)
frac ← a - intPart
fracBin ← ""
REPEAT 30 TIMES:
frac ← frac * 2
IF frac >= 1:
fracBin ← fracBin + "1"
frac ← frac - 1
ELSE
fracBin ← fracBin + "0"
ENDIF
END REPEAT
// 3. Normalise
IF intBin ≠ "" // number ≥ 1
E ← LENGTH(intBin) - 1
mantissaBits ← SUBSTRING(intBin,1) + fracBin // drop leading 1
ELSE // 0 ≤ a < 1
firstOne ← POSITION("1", fracBin)
E ← -firstOne
mantissaBits ← SUBSTRING(fracBin, firstOne) // bits after first 1
ENDIF
// 4. Biased exponent
e ← E + 127
expBits ← toBinary(e, 8) // pad to 8 bits
// 5. Fraction field (23 bits, round‑to‑nearest‑even)
fraction ← ROUND_TO_EVEN(mantissaBits, 23)
RETURN sign + " " + expBits + " " + fraction
END FUNCTION
For A‑Level work that demands greater accuracy, the double‑precision format uses:
| Field | Bits | Bias |
|---|---|---|
| Sign | 1 | — |
| Exponent | 11 | 1023 |
| Fraction | 52 | — |
The conversion steps are identical; only the exponent width, bias and mantissa length change.
0 10000010 01000000000000000000000 to decimal. Show each step and comment on any rounding.12.75 as a 32‑bit IEEE 754 binary pattern. Write pseudocode that performs the conversion and test it with this value.1 11111111 00000000000000000000000 represent? Explain why this pattern is special.
| Syllabus section | What to verify in the notes | Typical gaps & how to fix them |
|---|---|---|
| 1 Information representation (binary, BCD, hexadecimal, ASCII/Unicode, two’s‑/one’s‑complement, overflow) |
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| 1.2 Multimedia graphics (bitmap vs. vector, colour depth, resolution) |
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| 1.3 Compression (lossy vs. loss‑less, RLE, JPEG, MP3) |
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| 2 Communication (LAN/WAN, topologies, client‑server vs. peer‑to‑peer, thin/thick client, Ethernet/CSMA‑CD, IP addressing, DNS, IPv4/IPv6, subnetting, wireless vs. wired, cloud basics) |
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| 3 Hardware (components, RAM/ROM types, SRAM/DRAM, PROM/EPROM/E‑PROM, buffers, embedded systems, sensors/actuators) |
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| 3.2 Logic gates & circuits (NOT, AND, OR, NAND, NOR, XOR, truth tables, Boolean expressions, circuit construction) |
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