Construct a logic circuit

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3.2 Logic Gates and Logic Circuits (AO1‑AO3)

Learning Objectives (Cambridge AO)

  • AO1 – Knowledge: recognise symbols, write Boolean functions and truth tables for the seven basic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and for the four SR‑type flip‑flops.
  • AO2 – Application: construct a combinational circuit from a given Boolean expression or truth table, using the correct gate symbols.
  • AO3 – Analysis: verify a circuit by producing its truth table and, where required, optimise the circuit using Boolean algebra or Karnaugh‑map minimisation.

1. Logic‑Gate Reference

Gate Symbol Boolean Function Truth Table
AND AND gate $A\cdot B$
ABA·B
000
010
100
111
OR OR gate $A + B$
ABA+B
000
011
101
111
NOT NOT gate $\overline{A}$
A¬A
01
10
NAND NAND gate $\overline{A\cdot B}$
ABNAND
001
011
101
110
NOR NOR gate $\overline{A + B}$
ABNOR
001
010
100
110
XOR XOR gate $A\oplus B$ (true when exactly one input is 1)
ABXOR
000
011
101
110
XNOR XNOR gate $\overline{A\oplus B}$ (true when inputs are equal)
ABXNOR
001
010
100
111

Multi‑input Gates

All the gates above can be extended to three or more inputs. The symbol remains the same; extra input lines are added. Example: a 3‑input AND produces 1 only when all three inputs are 1.

2. Boolean Algebra – Rules You Must Know (AO3)

  • Identity: $A+0 = A$, $A\cdot1 = A$
  • Null: $A+1 = 1$, $A\cdot0 = 0$
  • Idempotent: $A+A = A$, $A\cdot A = A$
  • Complement: $A+\overline{A}=1$, $A\cdot\overline{A}=0$
  • Commutative: $A+B = B+A$, $A\cdot B = B\cdot A$
  • Associative: $A+(B+C) = (A+B)+C$, $A\cdot(B\cdot C) = (A\cdot B)\cdot C$
  • Distributive: $A\cdot(B+C)=A\cdot B + A\cdot C$, $A+(B\cdot C)= (A+B)\cdot (A+C)$
  • De Morgan’s Laws: $\overline{A+B}= \overline{A}\cdot\overline{B}$, $\overline{A\cdot B}= \overline{A}+ \overline{B}$

Quick Example (AO3)

Simplify $F = A\cdot\overline{A}+B\cdot C$

  1. Complement: $A\cdot\overline{A}=0$
  2. Identity: $0 + B\cdot C = B\cdot C$

Result: $F = B\cdot C$ – only one AND gate is required.

3. Karnaugh‑Map (K‑Map) Optimisation (AO3)

K‑maps give a visual method for minimising Boolean expressions with up to four variables.

Step‑by‑Step Procedure (3‑variable example)

  1. Write the truth table for the function.
  2. Transfer the output column (1’s and 0’s) into the K‑map cells, using Gray‑code ordering for the column/row headings.
  3. Form the largest possible groups of 1’s (sizes 1, 2, 4, 8). Groups must be rectangular and may wrap around the edges.
  4. For each group write the product term:
    • If a variable is the same (all 0 or all 1) in the group, include it (complemented if 0).
    • If a variable changes within the group, omit it.
  5. Combine the product terms with OR (+) to obtain the minimal SOP expression.

Worked Example

Minimise $H = A B \overline{C} + A \overline{B} C + \overline{A} B C + A B C$.

K‑Map for $H(A,B,C)$
BC
A00011110
00110
10111
  • Group 1 – the four 1’s covering columns 01 and 11 (both rows) → $B C$
  • Group 2 – the three 1’s in the bottom row (A = 1) covering columns 01, 11, 10 → $A C$ (B varies)

Minimal SOP: $H = B C + A C = C(B + A) = C(A + B)$.

Resulting circuit: one OR gate for $A+B$, one AND gate to combine the result with $C$.

4. Sequential Logic – SR‑type Flip‑Flops (AO1)

Flip‑Flop Symbol Inputs Outputs Characteristic Table
SR ⧖ S, R Q, $\overline{Q}$
SRQnext
00Q (no change)
010
101
11Invalid
JK ⧖ (J,K) J, K Q, $\overline{Q}$
JKQnext
00Q (no change)
010
101
11$\overline{Q}$ (toggle)
D ⧖ D Q, $\overline{Q}$
DQnext
00
11
T ⧖ T Q, $\overline{Q}$
TQnext
0Q (no change)
1$\overline{Q}$ (toggle)

These devices store a single bit and form the basis of sequential circuits such as counters, registers and memory units. In this unit they are used only for illustration.

5. Constructing a Logic Circuit – Full Procedure (AO2)

  1. State the specification: Write the Boolean expression or truth table that the circuit must satisfy.
  2. Simplify (AO3): Use Boolean algebra or a Karnaugh map to obtain a minimal SOP or POS form.
  3. Identify sub‑expressions: Break the simplified expression into individual logical operations (e.g., $A\cdot B$, $\overline{C}$).
  4. Select gates: Choose a gate for each operation. Remember:
    • AND + NOT = NAND (and vice‑versa)
    • OR + NOT = NOR (and vice‑versa)
    • Two NANDs in series can replace an AND‑gate with an inverted output.
  5. Draw the schematic:
    • Label all primary inputs (A, B, C …).
    • Place each gate using the symbols from the reference table.
    • Connect outputs of earlier gates to inputs of later gates exactly as the expression dictates.
    • Label intermediate signals (e.g., $A\cdot B$, $\overline{C}$) to aid verification.
  6. Verify (AO3):
    • Construct a truth table for the whole circuit.
    • Confirm that the output column matches the original specification.
  7. Optimise (optional): If the circuit uses more gates than necessary, revisit the Boolean‑simplification step or replace groups of gates with NAND/NOR equivalents.

6. Worked Example – From Expression to Circuit (AO2)

Task: Implement $F = (A\cdot B) + \overline{C}$.

Step 1 – Specification

Given Boolean expression: $F = (A\cdot B) + \overline{C}$.

Step 2 – Simplification

The expression is already minimal; no further reduction is possible.

Step 3 – Identify Sub‑expressions

  • $X = A\cdot B$ (AND gate)
  • $Y = \overline{C}$ (NOT gate)
  • $F = X + Y$ (OR gate)

Step 4 – Gate Selection

Use one 2‑input AND, one NOT, and one 2‑input OR.

Step 5 – Schematic

Circuit for F = (A·B)+¬C

Step 6 – Verification

ABC$A\cdot B$$\overline{C}$F
000011
001000
0

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