Lesson Plan

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Lesson Plan
Grade: Date: 25/02/2026
Subject: Computer Science
Lesson Topic: Show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors
Learning Objective/s:
  • Describe the key characteristics of RISC and CISC architectures.
  • Compare instruction set size, length, and pipeline suitability of RISC versus CISC.
  • Calculate CPU time using the performance equation and explain the impact of CPI.
  • Analyse how RISC and CISC designs affect parallel processing and virtual‑machine translation.
  • Evaluate the advantages and disadvantages of each architecture in real‑world contexts.
Materials Needed:
  • Projector and screen
  • Slide deck on RISC vs CISC
  • Handout with the comparison table
  • Whiteboard and markers
  • Laptops or computers with a CPU‑performance calculator
  • Worksheets for group activity
 Introduction:
Begin with a quick poll: which processor architecture powers most of today’s smartphones? Review prior knowledge of basic CPU components and the concept of an instruction set. Explain that by the end of the lesson students will be able to differentiate RISC and CISC designs and apply the performance equation.
Lesson Structure:
  1. Do‑now (5') – Students list known processor types and discuss perceived differences.
  2. Mini‑lecture (10') – Present RISC and CISC principles using slides and the comparison table.
  3. Guided practice (10') – Work through the performance equation with sample instruction counts for both architectures.
  4. Group activity (15') – Analyse the RISC vs CISC table, complete a worksheet identifying advantages/disadvantages and implications for pipelining.
  5. Demonstration (10') – Show a simple pipeline simulation for a RISC instruction and a CISC micro‑operation breakdown.
  6. Check for understanding (5') – Exit ticket: one sentence describing when a RISC design is preferable to CISC.
Conclusion:
Summarise that RISC offers simplicity and pipeline efficiency while CISC provides richer instructions and code density. Collect the exit tickets, address any lingering misconceptions, and assign homework to research a modern processor (e.g., ARM Cortex‑A78 or Intel Core i7) and write a short paragraph linking its architecture to the RISC/CISC concepts discussed.