Lesson Plan

• Describe the function of each stage in a classic 5‑stage RISC pipeline.
• Explain how a large register file supports pipelined execution and the load/store philosophy.
• Identify structural, data, and control hazards and evaluate mitigation techniques such as forwarding and branch prediction.
• Apply the load/store principle to differentiate RISC instruction types.
• Analyse a short instruction sequence to locate potential stalls and show how forwarding removes them.

• Projector and screen
• Whiteboard and markers
• Handout with a blank 5‑stage pipeline diagram
• Worksheet containing hazard identification tasks
• Laptops with a RISC simulator (e.g., MARS or similar)
• Printed register‑file reference chart
• Exit‑ticket slips or clicker system

Begin with a quick poll asking students how many instructions a CPU can execute per clock cycle, linking to their prior knowledge of the basic fetch‑decode‑execute cycle. Highlight that modern CPUs achieve higher throughput not by faster clocks but by overlapping work. State that by the end of the lesson they will be able to explain how pipelining and registers make this possible and how hazards are handled.

1. Do‑now (5') – short quiz on the classic instruction cycle to activate prior knowledge.
2. Mini‑lecture with slides (10') – introduce the five pipeline stages and the role of the register file.
3. Label‑the‑pipeline activity (10') – students annotate a handout diagram and discuss the purpose of each stage.
4. Hazard identification game (10') – groups examine a three‑instruction sequence, list structural, data, and control hazards.
5. Simulator demonstration (10') – show forwarding in action and how it eliminates stalls.
6. Guided worksheet (10') – students create a pipeline schedule for a new instruction sequence, applying hazard‑mitigation techniques.
7. Exit ticket (5') – each student writes one way forwarding or branch prediction improves performance.

Recap the five pipeline stages, the importance of a rich register file, and the three main hazard types with their mitigations. Collect exit tickets to gauge understanding, then assign a brief online quiz for homework that asks students to design a pipelined schedule for a given RISC code snippet and justify any forwarding used.