| Lesson Plan |
| Grade: |
Date: 25/02/2026 |
| Subject: Computer Science |
| Lesson Topic: Show understanding of how data are transferred between various components of the computer system using the address bus, data bus and control bus |
Learning Objective/s:
- Describe the roles of the address, data, and control buses in CPU communication.
- Explain how bus width influences addressable memory space and data throughput.
- Illustrate the fetch‑execute cycle, highlighting the interaction of the three buses.
- Compare unidirectional and bidirectional bus characteristics.
- Apply knowledge to identify bus signals in a given diagram or simulation.
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Materials Needed:
- Projector and screen
- Whiteboard and markers
- Printed handout of a CPU‑bus block diagram
- Worksheet for labeling buses and calculating addressable memory
- Computer with bus‑simulation software (e.g., Logisim)
- Sticky notes for quick‑write exit tickets
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Introduction:
Start with a short video of a city’s road network to draw a parallel with how data travels inside a computer. Prompt students to recall what they know about CPU components such as the ALU, control unit, and registers. Explain that today they will discover the three “highways” – address, data, and control buses – and will be able to trace a complete instruction fetch by the end of the lesson.
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Lesson Structure:
- Do‑now (5') – Quick quiz on CPU sub‑units (ALU, CU, registers) displayed on the board.
- Mini‑lecture (10') – Introduce the three buses with diagrams; discuss directionality and typical widths.
- Guided demonstration (12') – Use the simulation tool to run a fetch‑execute cycle, highlighting address, data, and control signals.
- Group activity (15') – Students label a blank bus diagram and calculate the maximum addressable memory for given bus widths.
- Check for understanding (5') – Exit ticket: each student writes one specific function of each bus.
- Summary discussion (8') – Review key points, answer questions, and connect bus concepts to real‑world hardware.
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Conclusion:
Recap how the address, data, and control buses cooperate during the fetch‑execute cycle and why their widths matter for performance and memory capacity. Collect the exit tickets to gauge individual understanding. For homework, assign a worksheet where learners design a simple bus layout for an 8‑bit microcontroller and justify their choice of bus widths.
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